Problems

Real physical-design tasks, the kind an engineer is actually handed, each graded by a tool run on the layout you produce. Grouped by the six Education topics, in flow order. This is the plan: the problem types below are being built out.

Logic Synthesis

8 problem types
Read the guide →

Technology-independent optimization

3

Shrink the Boolean logic before any library is chosen: fewer product terms, shared subexpressions, and no redundant gates.

Technology mapping

2

Cover the optimized network with real standard-cell library gates, trading area against delay.

Sequential optimization

2

Place and encode the state elements so the pipeline is balanced and the state logic is small.

Datapath synthesis

1

Choose the gate-level implementation of an arithmetic operator to hit the delay target at least area.

Floorplanning

19 problem types
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Macro placement

6

Position a block's hard macros on the die - the core skill of floorplanning. Each lab is a distinct chip and a distinct constraint, worked entirely in the browser: drag the macros, run the checks, place and route, and submit for a score.

Pin placement

2

Place a block's boundary I/O pins on the die edge so the nets to the logic that drives and receives them stay short.

  • DDR PHY pin placement interactive

    Place a DDR memory PHY's I/O pins on the die edge next to the byte lane, clock, or controller each one serves, to minimize wirelength and close the high-speed nets. Open the lab →

  • SerDes bus and I/O placement interactive

    The hard one: a wide SerDes die with two data buses that must each be packed as a contiguous block by their datapath, plus lane and clock pins, around fixed power pins. Open the lab →

Power grid design

7

Build the power delivery network that feeds the block without starving it or blocking the signal routing, then close it against the voltage-drop and reliability budgets.

  • Power ring and mesh sizing interactive

    Size the core power ring and the upper-metal stripe width and pitch so the network meets its static IR (current times resistance) drop budget without eating the routing tracks. Open the lab →

  • Regional mesh: per-domain IR drop interactive

    The hard one: a die split into power regions with different currents and different IR-drop budgets. Reinforce the mesh per region, since a uniform grid either starves the hot core or over-blocks the routing-heavy logic. Open the lab →

  • Standard-cell rail hookup interactive

    Size the metal-1 power rails and the via straps up to the mesh so every cell meets its local IR (current times resistance) drop without walling off the M1 tracks. Open the lab →

  • Power bump placement (flip-chip) interactive

    Place the power bump array that feeds the mesh from the package so current enters evenly and no region is starved of it. Open the lab →

  • Static IR-drop closure interactive

    Close a flagged IR-drop violation on a non-uniform current map by sizing the whole metal stack: lean on the cheap coarse top straps for the global drop and thread just enough routing-hungry mid straps for the local hotspots. Open the lab →

  • Decap insertion for dynamic droop interactive

    Place decoupling capacitors on the switching hotspots to hold the rail voltage during peak current, meeting the dynamic voltage-droop budget. Open the lab →

  • Electromigration-safe sizing interactive

    Widen the high-current stripes and grow their via arrays so the current density stays under the electromigration (EM) limit for the grid's rated lifetime. Open the lab →

Block sizing

1

Choose the die and core geometry before placement: area, aspect ratio, and how densely to pack.

Partitioning

1

Split the design into regions for hierarchy, keeping tightly-connected logic together so few nets cross the cuts.

Power domains

1

Floorplan multiple voltage domains: keep each domain contiguous and keep the level-shifter nets between them short.

Thermal

1

Place blocks so the die stays under its temperature limit while timing still closes.

  • Thermal-aware placement interactive

    Spread the high-power blocks to cool the hotspot while keeping the critical nets short: two hot blocks wired together can be neither too close nor too far. Open the lab →

Placement

12 problem types
Read the guide →

Global placement

5

Arrange the standard cells across the die - short wires, closed timing, and a routable density.

Clock-aware placement

1

Place with the clock network in mind, not just the data nets - group the flip-flops so the clock tree stays short.

Legalization

1

Snap the global-placement result onto the legal rows with no overlap, disturbing it as little as possible.

  • Row legalization interactive

    Drag the overlapping, off-grid cells onto the rows with no overlap and minimal displacement from their global spots. Open the lab →

Detailed placement

3

Local, discrete moves that shave the last of the wirelength after global placement and legalization.

Filler and tap insertion

1

The finishing pass after cells are placed and legalized: close the gaps and tie the wells so the rows are manufacturable.

Constrained placement

1

Place cells under region and fence constraints, not just for wirelength.

Clock Tree Synthesis

13 problem types
Read the guide →

Clock tree structure

6

Distribute the clock from the source to every flip-flop with balanced path lengths - the root of low skew.

  • Clock source balancing interactive

    Place the clock root so a star clock's path lengths to every sink are as equal as possible, minimizing skew. Open the lab →

  • H-tree construction interactive

    Position the tap points of an H-tree over a sink grid so every root-to-sink path matches, the classic zero-skew structure. Open the lab →

  • X-tree construction interactive

    The H-tree's diagonal cousin: balance four quadrant taps with straight-line (Euclidean) routing instead of right-angle segments. Open the lab →

  • Clustered buffer tree interactive

    Cluster irregularly-placed sinks and balance a buffered tree over them, compact clusters with equal arms - what a real CTS tool builds. Open the lab →

  • Clock mesh interactive

    Inject drivers into a shorted clock grid; the fewest, best-spread drivers that bring the covering radius (skew) under target, trading power for robustness. Open the lab →

  • Clock spine (fishbone) interactive

    Place a central spine and its drive point so the ribbed rows of sinks arrive balanced, the ASIC middle ground between tree and mesh. Open the lab →

Buffering and skew

3

Drive the tree cleanly and equalize arrival times across the sinks.

Clock power

2

The clock is often the largest power sink - cut its dynamic and switching power.

Advanced clock techniques

2

Trade skew deliberately and route the clock with special rules.

Routing

12 problem types
Read the guide →

Global routing and congestion

2

Decide the coarse routes and relieve congestion before the detailed router runs.

Layer and track assignment

2

Assign nets to metal layers and to tracks within a channel.

Detailed routing and design rules

6

Find the actual paths and lay the real geometry: shortest-path routing, design-rule clean, few vias, no antennas.

Special-net routing

2

The nets that need extra care: matched buses and crosstalk-sensitive signals.

Static Timing Analysis

11 problem types
Read the guide →

Slack and timing paths

4

The fundamentals: what slack is, the two checks, and the path that limits the clock.

Clocking

3

How real clock behaviour and timing constraints shape the analysis.

Variation and signal integrity

3

Sign-off across corners and the effects that steal timing margin.

Report literacy

1

Reading the timing report - most of the day-to-day STA job.

Physical Verification

10 problem types
Read the guide →

Design rule checks

4

The geometric rules a layout must obey to be manufacturable: width, spacing, enclosure, area, and density.

Layout versus schematic

2

Proving the extracted layout netlist matches the intended schematic: connectivity and devices.

Antenna and manufacturability

2

Charge-damage protection and yield-oriented recommended rules, checked before tapeout.

Electrical rules and sign-off

2

Electrical correctness and the final go / no-go gate before tapeout.

ECO

12 problem types
Read the guide →

Setup timing ECO

6

Speed up a path that arrives too late, in place, without changing the logic.

Electrical ECO

1

Fix electrical design-rule violations (max fanout, capacitance, and transition), not slack.

Hold timing ECO

1

Add delay so early-arriving data clears the hold requirement.

Clock ECO

1

Shift a clock arrival to move slack between stages.

Functional ECO

2

Change the logic itself with the least disturbance, metal-only where the spare cells allow it.

Placement ECO

1

Legalize ECO-inserted cells back onto the site grid with the least displacement.