Turn register transfer level code into a network of real library cells. Two jobs, in order: make the logic smaller while it is still abstract, then cover it with the cells the process actually has, trading area against delay.
Before any library is chosen, make the Boolean logic smaller: fewer product terms, shared subexpressions, and a structure that the mapper can cover well.
List every prime implicant of a function, then choose the fewest that cover all of its ones. Exact, and the yardstick every later minimizer is measured against.
Treat logic expressions as polynomials, find their kernels, and pull out the divisors that several expressions share. The core move of multilevel logic optimization.
Build all logic from two-input AND gates and inverters, then swap small subgraphs for smaller precomputed equivalents. The workhorse of open-source synthesis.
Cover the optimized network with standard cells from the library, so that every piece of logic is built exactly once, at the least area or the least delay the library allows.
Break the network into trees and cover each one with library gates by dynamic programming. Optimal on every tree, in time linear in its size.
Keep the best few small cuts at every node of the whole graph, map for minimum delay first, then recover area wherever the timing allows.