Floorplanning

What floorplanning is

Floorplanning is the first physical step of the flow. It fixes the size and shape of the die, the location of the large blocks and memories, the ring of input and output cells, and the power grid, all before a single standard cell is placed. It turns a synthesized netlist and a set of area and timing targets into a physical frame that every later stage works inside. Its decisions are expensive to undo, so the floorplan sets the ceiling on the quality the rest of the flow can reach.

The inputs and the die

A floorplan starts from the gate-level netlist, the area of every standard cell and macro, the timing constraints, and a target die. The engineer sets:

• the core area, where standard cells and macros go, and the die area around it that holds the input and output cells and the seal ring;
• the aspect ratio, the width-to-height ratio of the core;
• the utilization, the fraction of the core filled by cells.

Inside the core, standard cells do not float freely. They sit in rows of a fixed height, aligned to a grid of placement sites. Every cell in the library is built to that row height and to an integer number of site widths, so a cell fills a whole number of sites in one row, and the power and ground rails run horizontally along the row edges. The number of rows follows from the core height:

• core height the vertical extent of the core area
• row height the fixed height of a standard-cell row, set by the cell library

Placement, the power rails, and later legalization all snap to this row and site grid, so the die and core fixed here set the coordinate frame for everything that follows.

Aspect ratio and utilization

Utilization is the fraction of the core area occupied by cells:

• cell area the total area of the standard cells and macros to be placed
• core area the area available to place them in

It fixes the size of the die, and through that the two competing costs of the floorplan. A low utilization leaves wide gaps between cells: wires stay short and the router has spare tracks, but the die is large and each die costs more. A high utilization shrinks the die, but the same wires now share fewer routing tracks, so congestion rises and the router either detours signals or fails to finish. The floorplan sets the point where the design still routes and closes timing on the smallest die.

The size effect is direct. One square millimetre of cell area at 70 percent utilization needs a core of 1 / 0.70 = 1.43 square millimetres; raising utilization to 85 percent shrinks the core to 1.18 square millimetres, a 17 percent smaller die, while giving the router 15 fewer percentage points of empty area to route in. The starting value is chosen from how much routing the design demands:

Aspect ratio is the width-to-height ratio of the core:

• core width, core height the two side lengths of the core rectangle

A near-square core, with an aspect ratio close to 1, is the usual default: it keeps the longest cross-core wire short and balances the horizontal and vertical routing demand. A non-square ratio is chosen when the block must abut a neighbour of a fixed shape, fit a package outline, or carry a wide interface along one edge. An elongated core lengthens the standard-cell rows and the worst-case wire, which costs timing on the paths that cross the chip.

Macros and blocks

Hard macros, such as memories, analog blocks, and purchased IP (Intellectual Property), have fixed shapes and internal layouts. They must be placed deliberately, by hand or by a macro placer, before the standard cells. Their placement dominates the floorplan: a memory in the wrong corner forces long buses across the die and walls off routing behind it.

Three rules keep macro placement out of trouble:

Around each macro the floorplan adds a keepout halo, a margin no standard cell may enter. The halo reserves room for the macro's pins and their access, keeps cells off the edge where routing is densest, and leaves space to buffer the signals entering and leaving.

When many macros must fit a tight, fixed die outline, the floorplan is also a packing problem: the macros have to sit legally, with no overlap and none spilling past the outline, at high utilization. A common approach packs them into columns, largest first, filling each column before starting the next. Reaching the target utilization by leaving macros overlapping or outside the outline is not a legal floorplan, so packing density and legality are judged together with the quality rules above.

Partitioning

A large system-on-chip is too big to floorplan as one flat block, so it is split into a hierarchy of blocks that are floorplanned and implemented separately, then assembled at the top level. Partitioning decides that split.

The quality of a split is measured by its cut size: the number of nets that have pins in more than one block. Partitioning minimises the cut while keeping the block areas balanced, so that few connections cross between blocks and no single block dominates the die. Fewer crossing nets mean shorter top-level wiring and cleaner timing at the boundaries, where signals are slowest to close.

In practice the partition follows the design's register-transfer hierarchy, the functional blocks the design was written as, refined by how tightly parts are connected and how large each block should be. A good partition is balanced in size, has clean and narrow interfaces, and keeps high-bandwidth communication inside a block rather than across its edge. Each block is then assigned a region of the die, which is where partitioning meets the floorplan.

The power delivery network

Before cells are placed, the floorplan lays down the power grid: rings around the core, straps across it on the upper metal layers, and rails feeding the standard-cell rows. The grid is a hierarchy from wide upper metal down to the narrow rails, carrying current from the package into every cell. Two limits size it.

The first is the supply voltage lost in the grid's own resistance, the IR (current times resistance) drop:

• Vdrop the supply voltage lost between the package and the cell
• I the current drawn through that part of the grid
• R the resistance of the metal carrying it

The drop is budgeted to a small fraction of the supply, commonly a few percent, because a cell that sees a lower voltage switches more slowly and loses timing. A wider or denser grid lowers R and the drop. The second limit is electromigration: too high a current density in a wire slowly moves metal atoms over the chip's life and eventually opens the wire, so every segment has a maximum current density it must stay under.

Both limits push toward more and wider metal, but the power grid competes with signal routing for the same upper layers, so its density is a floorplan-level trade-off between a quiet supply and routable space.

The IR drop above is the static average. Current also swings sharply as blocks switch, and when demand spikes faster than the package and grid can respond, the local supply sags for a moment: dynamic voltage droop. Decoupling capacitors (decaps), placed as filler cells near switching logic, hold a small reservoir of charge that feeds these fast spikes locally until the grid catches up. Enough decap is budgeted into the floorplan to keep the droop inside the same voltage margin as the static drop.

The grid is not one uniform mesh. Different regions draw different current: a dense, high-activity block needs a tighter mesh than a quiet one. A uniform grid sized for the worst region wastes routing space everywhere else, and one sized for the average starves the hot spots, so the mesh density is set per region to that region's current and voltage-drop budget.

At the bottom of the hierarchy, the mesh straps drop through via arrays onto the thin metal-1 power rails that run along each standard-cell row, and every cell taps its rail. That last stretch of supply, from the nearest strap along the rail to the cell, is a local IR drop of its own, so the strap pitch is chosen so no cell sits too far from a strap.

Power domains and multi-voltage

Not all of a chip runs at one voltage. To save power, blocks that can tolerate it run on a lower supply, and blocks that are idle are switched off entirely. The floorplan groups the logic into voltage domains, each a contiguous region on its own power grid, so a whole domain can be supplied at a different voltage or powered down as a unit.

Special cells guard the domain boundaries:

Placing each domain as one contiguous region, with short boundaries and its special cells accounted for, is a floorplan decision. A domain scattered across the die needs a long, leaky boundary and a tangled power grid.

Thermal-aware floorplanning

Power turns into heat, and heat is not spread evenly: a block that switches hard, a processor core or a high-speed interface, is a hot spot. Temperature raises both transistor delay and leakage, and higher leakage raises temperature further, so a dense cluster of hot logic can run away. The floorplan spreads the heat by keeping the highest-power blocks apart rather than packing them together, and by leaving cooler logic or whitespace between them to carry heat away. This pulls against wirelength, which wants related hot blocks close, so thermal-aware floorplanning is a trade-off between a short net and an even temperature map.

Input and output placement

The input and output cells sit in the die periphery, or, for a flip-chip part, in an area array of bumps across the whole die. Their placement sets where signals enter and leave, so it constrains the internal layout. For a block inside a larger chip, the pin locations on its boundary are a contract with the parent design; placing each pin near the logic that drives or receives it shortens the top-level routing.

The pins of a bus belong together. A wide interface, a memory bus or a high-speed serial link (SerDes - Serializer/Deserializer), is placed as one contiguous block of pins on the boundary, right beside the datapath that drives it, so the whole bundle stays local and its bits can be kept length-matched. Scattering a bus's pins around the edge forces long, skewed top-level routes.

Two packaging styles set how the connections are made:

Most high-performance parts are flip-chip: the die is turned face-down and bonded through the bump array, which gives many more connections and, because power can enter anywhere across the area, a much stronger supply.

The flip-chip bumps are not spread evenly by default. Because the supply enters through them, the bump array is placed to match the chip's current map: more power bumps over high-current blocks, fewer over quiet ones, and none where a bump is disallowed, such as a keepout over a sensitive macro. A bump pattern that ignores where the current is actually drawn leaves a hot block starved even when the total bump count looks sufficient.

Placement blockages and regions

Blockages tell the placer where it may not put cells, and regions tell it where certain cells must go. Together they shape congestion and timing before placement begins.

Why the floorplan decides the flow

A floorplan is judged not by itself but by what it lets the rest of the flow achieve. A good one delivers:

• short reachable wirelength, so placement and routing start close to their targets;
• a routable congestion map, with routing tracks where the wires need them;
• a power grid that meets its voltage-drop and electromigration limits;
• macro and pin positions that let timing close without long detours.

Because every later stage works inside the frame the floorplan fixes, a weak floorplan cannot be rescued by good placement or routing, and its decisions are expensive to undo once cells are placed. That is why floorplanning, though it places nothing small, is the stage that most determines the final result.