What physical verification is
Physical verification is the set of checks that confirm a finished layout is manufacturable and correct before it is sent to the foundry. It comes after routing, on the final geometry, and it is the last gate before tapeout. Its two central checks are design-rule checking and layout-versus-schematic, supported by electrical, density, reliability, and lithography checks. A chip does not tape out until every one of them is clean.
Design rule checking
Design rule checking (DRC - Design Rule Check) verifies that the layout geometry obeys every rule the foundry publishes. The checker compares the drawn shapes against the rule deck and reports every violation by location and rule. Passing DRC means the shapes can be printed and will not short or open due to geometry.
A handful of rule families recur, and each is a thing the layout must get right:
| rule | what it requires | why |
|---|---|---|
| minimum width and spacing | every shape at least a minimum width, and at least a minimum gap to the next shape | narrower lines print unreliably; shapes too close short together |
| via enclosure | the metal on both layers must surround the via cut by a margin, not just touch it | a cut at the edge of its metal can miss the layer and open the connection |
| minimum area | each shape must cover at least a minimum area, not only meet the width | tiny slivers do not etch or fill reliably |
| width-dependent spacing | a wider wire needs a larger gap to its neighbours than a narrow one | wide metal couples more and blooms more in lithography, so it needs extra room |
| end-of-line (EOL) spacing | the tip of a narrow line needs extra clearance, and often extra via enclosure | line ends round off and pull back when printed, so they need a margin the sides do not |
At advanced nodes these multiply into thousands of interacting rules, but the families above are the ones a layout meets over and over.
Layout versus schematic
Layout-versus-schematic (LVS - Layout Versus Schematic) proves that the layout implements the intended circuit. It extracts a netlist from the layout geometry, extracts a reference netlist from the schematic or gate-level design, and compares the two device by device and net by net. A clean LVS means the silicon will connect exactly the transistors and nets the design specifies. A mismatch, an extra device, a swapped connection, a missing net, is a functional bug that must be fixed.
The comparison is not only about wiring. Each device must also match in type and size: a transistor with the wrong width, length, or threshold flavour is an LVS (Layout Versus Schematic) error even when it is connected correctly, because a differently sized device computes the same logic with the wrong drive, delay, or leakage. So LVS is both structural (the same devices wired the same way) and parametric (every device's properties agree with the schematic), which also underlies the analog demand that matched devices, such as the two halves of a differential pair, be laid out identically.
Antenna rules
During fabrication, metal is built one layer at a time, and a partially built wire connected only to a transistor gate can accumulate charge that breaks down the thin gate oxide. Antenna rules bound the ratio of connected metal area to gate area at each manufacturing step. Violations are fixed by adding a jog to a higher layer or a small protection diode. The figure shows the repair.
Electrical rule checks
Electrical rule checking (ERC - Electrical Rule Check) catches connectivity mistakes that are electrically illegal even if they pass geometric rules: floating gates, unconnected inputs, shorts between power and ground, and pins driven by conflicting sources. It is a lightweight but important guard against wiring errors that DRC and LVS alone might not flag.
A gate input that must hold a constant is not wired straight to a power or ground rail, because that ties a delicate transistor gate directly to the noisy supply and can stress it. Instead a tie-high or tie-low cell drives the constant through a small dedicated transistor, giving the gate a clean, protected fixed value. So the fix for an input that should be a constant is not "route it to the rail" but "insert a tie cell", and ERC flags both inputs left floating and, at some nodes, inputs tied straight to a rail instead of through a tie cell.
Density and metal fill
The foundry requires each layer's metal density to fall within a window, because chemical-mechanical polishing planarizes better on a uniform surface. Sparse areas are filled with electrically inert metal shapes, and over-dense areas must be relieved. Fill is inserted late and then re-checked, because it changes the parasitics that timing signed off on, so it is added with awareness of the sensitive nets.
Lithography and manufacturability
At advanced nodes the drawn shape and the printed shape differ, so manufacturability checks go beyond fixed spacings. Lithography-friendly rules, recommended patterns, and multi-patterning color constraints all constrain what may be drawn, and design-for-manufacturing checks flag patterns that would print poorly or yield badly. The figure shows the resolution limit that drives these rules.
A common design-for-manufacturing improvement is via doubling. A single via can fail to form during fabrication, or crack over the chip's life, and either way it opens the net. Where the layout has room, the tool replaces a lone via with two or more cuts in parallel, a redundant via, so the connection survives if one cut fails. It changes no logic and is inserted late wherever space allows, raising yield and long-term reliability.
Reliability sign-off
Beyond geometry and connectivity, the layout is checked against the physical limits that govern how long the chip survives. Electromigration limits the current density a wire may carry before it degrades, and IR (current times resistance) drop limits how far the supply voltage may sag under load. These reliability checks run on the extracted power grid and signal wires and must pass across the operating corners.
Sign-off and tapeout
Physical verification is the convergence point of the flow. Only when DRC, LVS, antenna, electrical, density, lithography, and reliability checks are all clean, across every required corner, is the design signed off and the final layout, as a GDSII (Graphic Data System II) or OASIS file, sent to the foundry. Everything upstream exists to reach this clean state.