Interface (I/O) timing

Interface (input/output) timing. Register-to-register paths live entirely inside the chip, but an I/O path is only partly yours. Part of the clock period is spent off-chip, and STA (static timing analysis) captures that with set_input_delay / set_output_delay (specified relative to a clock, often a virtual one that models the far device):

• Input path: off-chip launch (the source's clock-to-Q plus board routing = the input delay) + your internal logic + capture setup.
• Output path: your clock-to-Q + your internal logic + the output delay (the far device's setup plus board routing).

The clock period is fixed. Each interface path is drawn as a budget bar against the capture edge. For every path, pick the cheapest fix that makes it fit:

• Leave it if the bar already fits.
• Optimize the logic when your internal logic is the bottleneck (this shrinks the internal segment to its floor).
• Register the boundary port (a flop at the pin) only when the off-chip delay is so large the path cannot fit even with optimized logic. This breaks the external delay off the internal budget, but it costs one extra cycle of latency, so do not use it where optimizing would have been enough.

Aim each fix at the real bottleneck (read the budget split), then Submit fixes. Over-fixing (registering when optimizing would do) is marked wrong.