Manual macro placement

A RISC-V CPU core block: 15 hard macros - caches, register files, the execution core, and peripherals - dropped in a random start position. Arrange all 15 so the three checks pass.

• Timing closed - every critical net (bold) under its budget. Anchor the blocks to their interfaces: the l2$ to the memory bus, the exec core to the L2 controller, the integer register file iregs to the clock, and the lsu to the peripheral bus. Keep tightly-coupled blocks close (alu with fpu, the two register files together).
• Legality - every macro inside the core with a keepout halo (no red).
• No congestion overflow - keep the routing-demand map out of the red.

Drag, Run analysis until all green, Place & Route, Submit.