Technology mapping: area vs delay

Technology mapping: area vs delay. The smallest mapping is not always the right one. The circuit is a wide AND: ten 2-input AND gates chained into an 11-input AND. Mapping groups the chain into library AND cells, where a group of k gates becomes one AND(k+1) cell (up to AND4). A wider cell does more in a single logic level, so it is faster, but it costs more area. The output arrival is the sum of the cell delays along the chain, and it must meet a target.

The cheapest mapping, every gate its own AND2, is too slow. The fastest, all AND4, over-spends area for speed the target does not need. The right answer widens the cells just enough to meet the target.

Click a boundary between two gates to merge them into one wider cell, or split again. Meet the arrival target at the least area, then Submit mapping. This is why the cost function is an input to synthesis: the same logic maps to a different netlist when the block is timing-limited rather than area-limited.