SerDes bus and I/O placement

A 4-lane SerDes transceiver on a wide die: a much harder I/O-planning job. The internal macros are placed and locked (hatched): the transmit and receive datapaths (tx_dp, rx_dp) on the left, two clock PLLs, the centre mac, and four high-speed lanes (serdes0-serdes3) on the right. Two power pins (vddh0, vss0, grey) are fixed and will not move. You place the 16 I/O pins, which start spread around the boundary.

The new twist is buses. The transmit bus (txb0-txb4) is a single net to tx_dp, and the receive bus (rxb0-rxb4) a single net to rx_dp. A bus is only short when all five of its pins sit together next to their datapath, so each must be packed as a contiguous block on the left edge beside its macro, the transmit bus up by tx_dp and the receive bus down by rx_dp.

• Timing closed - the two bus nets and the six single high-speed nets (bold) under budget. Group each bus against its datapath, put each lane's hs pin beside its lane, and each ck by its PLL.
• Legality - every pin on the die edge, a pitch apart, and clear of the two fixed power pins.
• No congestion overflow - a scattered bus fans a thick bundle of wires across the die. Grouping each bus by its macro keeps the demand local.

Drag the pins, Run analysis, Place & Route, Submit.