Synthesizing a block, end to end
Turn a register transfer level description into the gate-level netlist the rest of the flow works on. The design is tile4m, a small teaching
block: four memory macros, a controller for each, and a hub that ties
them to the pins. One design, carried through every stage.
The commands here are
OpenROAD's,
one open-source flow. The steps are common to physical design
everywhere, and so are the questions each one asks. The command names,
the arguments, and the defaults are not: a commercial tool does the same
work with its own commands, and a different flow may split or merge these
steps. Read the commands as one worked example, not as the way it is
always done.
Other stages of the flow: Floorplanning · Placement · Clock Tree Synthesis · Routing · Timing Analysis · Finishing