Static Timing Analysis

What static timing analysis is

Static timing analysis is how the flow proves that a synchronous design meets its clock, across every path, without simulating a single input vector. Instead of applying stimulus and watching signals settle, it reasons about delays directly on the circuit's structure. That is what static means: the answer does not depend on the data flowing through the chip, only on the timing of its gates and wires. It is the final arbiter of whether a chip is fast enough to ship, and the inner-loop oracle every optimization step consults.

It runs on four inputs:

• the netlist, the gates and the connections between them;
• the timing libraries, giving every gate's delay as a function of input transition time and output load;
• the constraints, chiefly the clock definitions and the timing of the chip's inputs and outputs, written in SDC (Synopsys Design Constraints);
• the parasitics, the resistance and capacitance of the wires, extracted from the layout once it exists.

From those it produces one number at every point in the design, the slack, and a verdict for every sequential endpoint: met or violated. The rest of this page develops all of that in full, from the graph at its core through the delay models, clock effects, constraints, and variation layers that make the numbers trustworthy at sign-off.

The timing graph

Static timing models the design as a directed graph. Nodes are pins. Edges are timing arcs carrying a delay: a gate arc from an input to an output, and a net arc from a driver to its sinks. Two quantities propagate through it. The arrival time of a node is the latest a signal can reach it; the required time is the latest it may arrive and still meet the clock. Their difference is the margin at that node.

• slack the timing margin: positive means met, negative means violated
• required the latest allowed arrival, swept backward from the constraints
• arrival the worst-case arrival, swept forward from the clocks

Two linear sweeps compute it for the whole design. A forward sweep sets each node's arrival to the maximum over its incoming edges, so the slowest path always wins. A backward sweep sets each node's required time to the minimum over its outgoing edges. One subtraction per node then gives slack, and the minimum-slack chain is the critical path. The figure sweeps a small graph both ways.

The power of this is that the number of paths can be astronomical, but one arrival value per node summarizes every path reaching it, so two sweeps that are linear in the circuit size replace an impossible enumeration.

Slew (transition time) propagates through the same graph, and it is not just along for the ride: it is what the delays are computed from. A gate arc's delay depends on the slew arriving at its input and the load on its output, so the timer must know a node's input slew before it can find the arc's delay. The forward sweep therefore carries slew and arrival together: each arc turns its input slew and load into an output slew, that output slew becomes the next stage's input slew, and the same numbers give the delay that advances the arrival. Slew moves forward only; the backward required-time sweep does not need it. Rising and falling edges propagate as separate values, and the min and max corners attach as extra tagged values, all without changing the two-sweep structure.

Setup and hold: the two checks

A flip-flop captures its data input only if that input is stable across a small window around the clock edge: the setup time before the edge and the hold time after it. On a path from a launch flip-flop through logic to a capture flip-flop, those two library numbers become two checks.

• T the clock period, the time to the next capture edge
• tsu, thold the capture flip-flop's setup and hold times
• arrivalmax latest data arrival, from the slowest path
• arrivalmin earliest data arrival, from the fastest path

The asymmetry drives everything downstream. Setup is the late check: it uses the maximum path delay and measures data against the next clock edge, so a longer period buys margin. Hold is the early check: it uses the minimum path delay and measures data against the same edge, so the period cancels and no clock setting can fix a hold violation. The figure shows the aperture and then each check in turn.

Because the two pull in opposite directions, a legal path must satisfy both at once: speeding a path up helps setup and hurts hold, and adding delay does the reverse. Setup dominates the target-frequency question and is optimized throughout the flow; hold is closed late, after the clock tree and routing fix the real delays, by inserting delay on the fastest paths.

Timing paths and path groups

Every check lives on a timing path: a start point where a value is launched and an end point where it is captured. Start points are primary inputs and register clock pins; end points are register data pins and primary outputs. That gives four kinds of path the timer must constrain:

The timer collects paths into path groups, usually one per clock plus a group for the input/output paths, so the report and the optimizer can treat each clock domain on its own. A path that crosses from one clock to another is analyzed against the relationship between those two clocks, which is why clock definitions matter so much.

The interface paths, input-to-register and register-to-output, are budgeted against the logic outside the block. That external logic is modeled with an input or output delay relative to a virtual clock: a clock with no physical pin that stands in for the timing of the off-chip or neighbouring device. The interface budget is shared: whatever the outside logic consumes, the block does not have. When an interface path will not close, one option optimizes the internal logic, and another registers the boundary port, placing a flip-flop right at the input or output. That turns a long input-to-register or register-to-output path into a short one plus a clean register-to-register path, reclaiming clock frequency, at the cost of one extra cycle of latency through the interface. Trading latency for frequency this way is a common interface-timing decision.

Slack, WNS, and TNS

Slack is computed per endpoint, but a design has millions of them, so two summary numbers describe its timing health:

• WNS (Worst Negative Slack): the single worst slack in the design. It answers "how badly is the worst path failing?" and sets the frequency the design can actually run at.
• TNS (Total Negative Slack): the sum of the negative slacks over all failing endpoints. It answers "how much failure is there?" A design can have a small WNS but a large TNS if many endpoints fail by a little, which is a different repair problem than one deep violation.

Both are reported per path group and per corner, and both must be clean across the whole MCMM matrix before a chip signs off.

Delay calculation and library models

The edges of the graph get their numbers from delay calculation, and this is where accuracy is won or lost. A cell arc's delay is not a constant: it is a function of two variables, the input transition time (slew) and the output load the cell drives. A sharper input edge and a lighter load give a faster arc.

• NLDM (Non-Linear Delay Model) stores each arc as a two-dimensional lookup table indexed by input slew and output capacitance, with the timer interpolating between entries. It returns both the arc delay and the output slew, which becomes the next stage's input slew. It is the standard delay model for older nodes.
• Effective capacitance is the fix NLDM needs on real wires. A resistive interconnect shields the far capacitance from the driver, so the cell does not see the full lumped load. The timer iterates a single effective capacitance that reproduces the true output waveform.
• CCS (Composite Current Source) and ECSM (Effective Current Source Model) replace the single delay number with the cell's output modeled as a current source over time. Capturing the waveform shape, not just a delay point, makes them far more accurate on the resistance-dominated loads and noise analysis of advanced nodes.

The interconnect itself is a circuit. Extraction turns each net into a resistance-capacitance network, and the timer reduces that network to a delay and an output slew, first order by the Elmore delay and more accurately by higher-order moment matching. Slew degrades as it propagates, so a poorly buffered net hurts every stage downstream of it, not just its own delay.

Clocks: latency, skew, jitter, and uncertainty

Before the clock tree is built the timer treats the clock as ideal, reaching every flip-flop at the same instant. After clock tree synthesis it uses the propagated clock, through the real tree, and several clock effects enter the checks:

• Latency is the delay from the clock source to a flip-flop, split into source latency (off-chip and up to the definition point) and network latency (through the on-chip tree).
• Skew is the difference in clock arrival between the launch and capture flip-flops. It shifts the checks directly, and in opposite directions for the two checks.
• Jitter is cycle-to-cycle variation in the clock edge, mostly from the phase-locked loop generating it.
• Uncertainty is a lumped margin (set by set_clock_uncertainty) that folds jitter and extra guard-band into a single number, subtracted from the setup window and added to the hold window.

Writing the setup check with these terms shows how skew helps or hurts:

• T the clock period
• skew capture-clock latency minus launch-clock latency (positive helps setup)
• tck→q the launch flip-flop's clock-to-output delay
• delaymax the slowest combinational path delay
• tsu, uncertainty the setup time and the clock uncertainty margin

The same skew that adds to setup slack subtracts from hold slack, which is why a clock tree that helps one check can break the other, and why useful-skew optimization is done carefully against both.

More sequential checks

Setup and hold are the common pair, but the timer runs several more checks on sequential and clock structures:

• Recovery and removal are the setup and hold of asynchronous set and reset pins: the deassertion of an async control must clear the clock edge by a recovery time (like setup) and hold past it by a removal time (like hold).
• Minimum pulse width and minimum period ensure a clock's high and low phases are wide enough for the flip-flops and that the period is legal for the library.
• Clock-gating checks time the enable signal at a clock gate so the gated clock never produces a partial or glitched pulse.
• Latch timing and time borrowing: a level-sensitive latch is transparent while its clock is active, so data may arrive after the opening edge and still be captured. That lets a slow path borrow time from the next stage's budget, a flexibility flip-flops do not have and a bookkeeping the timer must track across phases.

Constraints (SDC): defining the problem

The timer only knows what the constraints tell it, so the SDC (Synopsys Design Constraints) file is half the analysis. The core commands define the clocked world:

• create_clock defines a clock's period and waveform on a port or pin; create_generated_clock derives dividers, multipliers, and multiplexed clocks from it.
• set_input_delay and set_output_delay model the timing of logic outside the block, relative to a clock, so the input-to-register and register-to-output paths are constrained.
• set_clock_latency and set_clock_uncertainty supply the clock numbers above.

On top of that sit the exceptions, which tell the timer where the default single-cycle assumption is wrong:

The danger runs both ways. A missing false-path or multicycle exception makes the timer report violations that cannot happen, wasting effort chasing impossible paths. A missing or wrong constraint leaves real paths untimed, so the design can pass analysis and fail in silicon. Constraint quality is its own discipline.

Corners and modes (MCMM)

A single analysis is not enough, because delay depends on manufacturing and environment. The libraries are characterized at PVT corners: combinations of Process (fast or slow silicon), Voltage, and Temperature. Slow-process, low-voltage, high-temperature conditions generally make gates slow and stress setup; the fast, high-voltage, cold corner makes them fast and stresses hold. Advanced nodes add temperature inversion, where cold can be the slow case, so corners are chosen from characterization rather than assumed. Interconnect adds its own resistance-capacitance corners.

Alongside corners are modes: functional, test, scan, and low-power modes, each with its own constraints. MCMM (Multi-Corner Multi-Mode) analysis evaluates every enabled corner-and-mode scenario, and sign-off requires that all of them pass. Setup is dominated by the slow corners, hold by the fast, so a design is genuinely closed only when the whole matrix is clean.

On-chip variation and pessimism removal

Even within one die, no two transistors are identical, so a single corner is optimistic about the difference between two paths on the same chip. OCV (On-Chip Variation) models this by derating: slow the data path down and speed the capture clock path up for a setup check, and the reverse for hold, so the check sees a pessimistic split.

Flat derating over-counts, and two refinements pull the pessimism back:

• CPPR (Common-Path Pessimism Removal): the launch and capture clocks share a common segment of the tree. Derating that shared segment in opposite directions is physically impossible, so the timer credits the double-count back. This is often the difference between a false hold failure and a real one.
• AOCV (Advanced OCV) and POCV (Parametric OCV) make derating depend on the statistics of the path rather than a flat factor. A deeper path averages out more variation, so it needs less margin; parametric OCV assigns each cell a single sigma and combines them statistically. Both cut the pessimism of flat OCV while staying conservative.

Fully statistical timing, SSTA (Statistical Static Timing Analysis), carries delay distributions through the graph and reports a slack distribution and a yield. It is the most rigorous treatment of variation but the heaviest, and in practice corner-based analysis with parametric OCV is the common industrial choice.

Crosstalk and signal-integrity timing

Neighboring wires couple through capacitance, so a switching aggressor net injects charge onto a quiet or switching victim. The timing effect is a delta delay: if the aggressor switches the same way as the victim it speeds the victim up, and if it switches the opposite way it slows it down. A stable victim can also see a noise glitch large enough to be captured as a wrong value.

Signal-integrity-aware timing computes these delta delays and folds them into the path delay, using timing windows to decide which aggressors can actually align with the victim's transition. It matters most on long, tightly packed routes at advanced nodes, and it is a mandatory part of sign-off there.

Static timing in the flow and at sign-off

The same computation appears in two guises. Inside synthesis, placement, clock tree synthesis, and routing it runs incrementally as the optimizer's oracle: fast, approximate, and re-evaluated after every local change so the tool knows whether a move helped. At the end it runs as sign-off: accurate delay models, extracted parasitics, the full multi-corner multi-mode matrix, signal-integrity delta delays, and pessimism removal, on the final layout.

Closing timing means driving WNS (Worst Negative Slack) to zero or positive and keeping TNS (Total Negative Slack) under control at every corner and mode, with hold fixed after the clock and routing are real. The last iterations are targeted engineering-change-order fixes, guided by exactly the slack reports this page has built up. Everything in static timing analysis either feeds this graph better numbers or reads its slack report more precisely.

Reading a timing report

A timing report (in the open flow, report_checks in OpenSTA) prints one critical path at a time as a running sum. Read it as three parts:

1. The header: the start point, the end point, the path group, and the analysis type (max for setup, min for hold).
2. The data path: a point-by-point accumulation of delay from the launch clock edge through each gate and net to the endpoint's data pin, ending in the data arrival time.
3. The clock and constraint side: the capture clock edge, plus or minus clock latency and uncertainty, and the setup or hold time, giving the data required time.

The last line subtracts the two into slack and prints MET or VIOLATED. Learning to read this accumulation, and to see which gate or net is eating the budget, is the core skill of timing closure and the reason every section above matters in practice.