What placement is
Placement assigns every standard cell a legal location in the rows of the core, taking the floorplan as fixed. It is where the netlist becomes a physical arrangement, and it decides most of the wirelength, and therefore most of the delay and power, before routing runs. A modern block has millions of cells, so placement is a large numerical optimization, not a hand process.
Wirelength: the objective
The quantity placement minimizes is total wirelength, estimated for each net before routing exists by its half-perimeter wire length:
HPWLthe Half-Perimeter Wire Length of one netxmax, xminthe extreme pin x-coordinates on the netymax, yminthe extreme pin y-coordinates on the net
The half-perimeter of the bounding box is exact for two- and three-pin nets and a good estimate otherwise, and summed over all nets it is the placer's cost. Minimizing it pulls connected cells together while density limits push them apart.
Global placement
Global placement finds an approximate, slightly overlapping arrangement that minimizes wirelength subject to spreading cells out. Two families dominate. Analytical placers model wirelength and density as smooth functions and solve for the minimum, either by quadratic optimization with a spreading force, or by nonlinear solvers on modern GPU-accelerated tools. Force-directed placers treat nets as springs pulling cells together against a repulsive density force. Both end with cells roughly where they belong but not yet on legal sites.
Legalization
Legalization snaps the overlapping global-placement result onto legal standard-cell sites in the rows, moving each cell as little as possible so wirelength is barely disturbed. Cells sit in fixed-height rows aligned to the power rails, and legalization removes overlaps and off-grid positions. The figure shows cells resolved into rows.
Detailed placement
Detailed placement is a local cleanup pass on the legal result, recovering the quality legalization had to give up, without breaking legality. It has a few distinct moves:
- swapping two neighbouring cells, when trading their positions shortens the nets through them;
- sliding a cell along its row into nearby whitespace;
- flipping a cell's orientation. Mirroring a cell left-to-right swaps which edge its input and output pins sit on, so a pin can be turned to face its partner across the net and shorten the connection.
It can also pad a cell, reserving a little extra space beside a pin-dense cell so the router has room to reach every pin. Padding relieves a local pin-access hotspot at the cost of a little area, so it is applied only where pin access is tight, not across the whole block.
Density and congestion
Wirelength alone would pile cells into a heap, so placement enforces a density limit per region and, in congestion-aware mode, spreads cells out of areas the router would overflow. A congestion map (estimated by a quick trial global route, or by an analytical measure) tells the placer where to open space. Trading a little wirelength for routability here prevents unroutable hotspots later.
Timing-driven placement
Pure wirelength does not know which nets are timing-critical. Timing-driven placement weights nets by their timing slack, pulling the cells on critical paths closer while letting slack paths stretch. It runs static timing incrementally as it places, so the arrangement is optimized for the paths that actually set the clock, not just for total wire.
Clock-aware placement
A register's position decides how far the clock has to travel to reach it. If the flip-flops that share a clock are scattered across the block, the clock tree that serves them is long: more buffers, more power, and harder to balance for skew. Clock-aware placement pulls the registers of a clock into tighter clusters as it places them, shortening the tree that clock tree synthesis will later build on top of the placement. It trades a little data-path wirelength for a smaller, lower-power, easier-to-balance clock, so it is placement done with the next stage in mind.
Mixed-size placement
When movable macros sit alongside standard cells, the placer must handle both scales at once. Mixed-size placement floats the macros during global placement, then fixes them and places the sea of cells around them. Getting the macro and cell placement to agree is the hardest part of placing a modern block, and it links placement back to the floorplanning decisions above.
Filler and tap cells
When the real cells are placed, gaps remain between them in the rows, and two kinds of always-present cells fill those gaps. Filler cells are dummy cells with no logic that continue the power rails and the wells across the gaps, so each row stays electrically continuous and manufacturable; the decoupling-capacitor fillers from the power work sit here too. Tap cells (well taps) tie the wells and substrate to the supply and ground at a regular pitch, which a design rule requires: no transistor may be farther than a fixed distance from a tap, or the chip risks latch-up. Both are inserted after placement on a fixed spacing, and both are checked again at physical verification.
Placement regions and constraints
Sometimes the placer must be told where certain cells may or may not go. A region (or guide) pulls a named group of cells toward a chosen area without forbidding other cells from sharing it. A fence is exclusive: it reserves an area for one group and keeps every other cell out. These constraints keep a functional block, a power domain, or a datapath together, or hold cells away from a sensitive area, so the placer still minimizes wirelength but does it inside the boundaries the floorplan set, not freely across the whole die.
Placement and the downstream flow
Placement hands routing a congestion map it must live with and hands timing the delays it will try to close. A placement that ignores congestion routes badly, and one that ignores timing closes slowly. Because it sets wirelength, placement is the largest single lever on power and performance after the floorplan, and every later stage is shaped by it.