Bus length matching

Bus length matching. You do not length-match every bus. It matters for a matched group of signals that are captured together - above all a source-synchronous bus, such as a DDR memory byte lane, where the data bits are sampled against a forwarded strobe (DQS), so skew between the bits eats the timing window directly. SerDes pairs and other clock-forwarded interfaces need the same. The router is handed the group as a length- (or delay-) match constraint and tunes the bits to meet it.

Ordinary on-chip nets are not length-matched: each is timed on its own by static timing analysis, and buffering fixes the slow ones. Here you tune one matched group.

• Skew within tolerance - the bus leaves a common driver and each bit ends at a receiver. Click a bit to fold in a serpentine detour (the real "trombone" tuning trick) that lengthens it. Bring every bit within the skew tolerance of the longest bit.
• Add as little extra wire as you can.

Match the group, then Submit design.