What the fab hands a physical-design engineer and how it constrains every stage of the flow: the PDK (Process Design Kit) and its libraries, the transistors and the metal stack, the lithography that sets the pitches, the variation and reliability limits that define sign-off, and the open PDKs this platform runs on.
Read this first. A PDK (Process Design Kit) is the contract between the fab and the design team: every geometry the tools may draw, every cell they may place, and every rule and model they must obey come from it.
The files a foundry ships and what each one tells the flow: technology rules and layers, cell geometry, timing and power models, verification decks, and parasitic tables.
Fixed-height, variable-width logic cells on a common site grid, characterized into timing and power tables: the vocabulary every digital design is written in, and the geometry that placement and routing take as given.
The layers a process offers, their pitches and preferred directions, and the width, spacing, enclosure, and area rules that make a shape manufacturable: the constraints the router and the DRC (Design Rule Check) deck agree on.
The switch itself, and how its shape changed as it shrank: planar, FinFET, and gate-all-around, and why the node name stopped meaning a dimension.
How the MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) changed shape to keep switching off as it shrank: planar to FinFET (2011) to gate-all-around nanosheets (2022), and what each shape means for cell design.
Node names stopped tracking any physical dimension around the 22 nm generation. What actually defines a node: gate pitch, metal pitch, fin or sheet pitch, cell height, and the density metric that follows from them.
Ten to fifteen metal layers above the transistors, each with a pitch, a thickness, and a resistance. Routing uses these layers, and at advanced nodes so does most of the delay.
The back end of line builds the interconnect one layer at a time by dual damascene: etch trenches and via holes into dielectric, line and fill with copper, polish flat. The process order is why vias, fill, and antenna rules exist.
Shrinking a wire raises its resistance faster than it lowers its capacitance, so wire delay grew as gate delay fell. The RC (Resistance-Capacitance) arithmetic, and the consequences: buffering, layer promotion, and timing that depends on routing.
How patterns get onto the wafer sets what the router may draw: the resolution limit, multi-patterning, EUV (Extreme Ultraviolet), and the design-for-manufacturing rules that follow.
One exposure prints features no finer than a limit set by wavelength and optics. Immersion 193 nm reached that limit around 80 nm pitch; everything finer needed multiple patterning until EUV (Extreme Ultraviolet) arrived, and the router inherits the constraints of whichever is used.
Rules that trade yield rather than legality: recommended spacings, redundant vias, metal fill, and lithography hotspot avoidance. Passing DRC (Design Rule Check) makes a layout manufacturable; DFM makes it manufacturable often.
No two transistors are identical and no wire lasts forever. Corners, on-chip variation, electromigration, and IR (current times resistance) drop are how the flow guarantees a chip that works across the full distribution, for years.
Transistors vary with manufacturing, supply voltage, and temperature. Sign-off proves timing at the extreme combinations, the corners, and modern flows check dozens of them, each with its own Liberty tables and parasitics.
Corners bound die-to-die variation, but two paths on the same die also differ. OCV (On-Chip Variation) derates launch and capture paths in opposite directions; AOCV and POCV refine the pessimism by depth and by statistics.
Two failure modes of the power and signal wires: electromigration, where current slowly moves metal atoms until a wire opens or shorts, and IR drop, where resistance in the supply network lowers the voltage cells actually see. Both are checked at sign-off and both shape the power grid.
The process kits anyone can download, and the ones this platform's graded problems actually run on.
Manufacturable process kits published under open licenses, with real fabrication available through shuttle programs. SKY130 is the process this platform's graded problems run on.
A fictional but realistic 7 nm FinFET process kit for research and teaching: EUV (Extreme Ultraviolet) single exposure on critical layers, fin-quantized libraries, a 9-layer stack. Not manufacturable, but the only open place to see advanced-node structure end to end.