CTS
Clock Tree Synthesis
Building the network of buffers and wires that delivers the clock to every flip-flop, aiming to keep the arrival times close together.
Reference
Glossary
Every term and acronym the site uses, defined once. Each entry links to the pages that use it, found by searching the site's own content, so the links follow the pages rather than being kept up to date by hand.
108 of 108 terms
The flow
The stages a design passes through, and the words for what comes in and out of each.
ECO
Engineering Change Order
A small, targeted change to a design late in the flow, made without rerunning every stage. A metal-only change after tapeout reuses the transistor masks and is far cheaper than a full respin.
EDA
Electronic Design Automation
The software used to design and verify chips, from synthesis through placement, routing and sign-off.
Floorplanning
Deciding the size and shape of the die and core, where the macros go, where the pins are, and how the power grid is laid out, before any standard cell is placed.
IP
Intellectual Property
A reusable design block licensed or shared for use in other chips, such as a processor core or an interface.
Appears in: Floorplanning
Logic synthesis
The step that turns RTL (Register Transfer Level) into a netlist of cells from a specific library, optimizing for area, delay or power along the way.
Appears in: Logic Synthesis
Macro
A large pre-built block placed as a single unit, such as a memory. It occupies the lower metal layers across its footprint and exposes its connections as pins on its edge.
Netlist
A list of cell instances and the nets that connect their pins. It describes what is connected to what, but not where anything is.
PDK
Process Design Kit
The files a foundry provides to design in its process: device models, design rules, layer definitions and usually standard-cell libraries.
Placement
Deciding where every standard cell sits. Global placement spreads cells to shorten wires within a density limit; legalization and detailed placement then snap them onto legal sites without overlap.
PPA
Power, Performance, Area
The three measures a physical design is usually judged by, and the trade-off between them.
Appears in: PD fundamentals flash cards
Routing
Drawing the metal wires and vias that implement every net. Global routing plans which regions each net passes through; detailed routing draws the actual shapes on legal tracks.
RTL
Register Transfer Level
A description of a digital design in terms of registers and the logic that moves data between them on each clock edge, written in a hardware description language such as Verilog. It is the input to logic synthesis.
Sign-off
The final set of checks, on timing, power and physical rules, that a design must pass before it is released for manufacture.
SRAM
Static Random-Access Memory
Memory that holds each bit in a small cross-coupled latch and keeps it as long as power is applied. On a chip it is usually a macro produced by a memory compiler.
Standard cell
A small, pre-designed logic gate or flip-flop of fixed height, built so that cells can be placed side by side in rows and share supply rails. A standard-cell library is the set of these a design is built from.
Tapeout
Releasing the final layout to the foundry for mask making. The name comes from the magnetic tape the data was once delivered on.
Timing
How a design is checked against its clock, and the numbers that report it.
AOCV
Advanced On-Chip Variation
A refinement of OCV (On-Chip Variation) that scales the derating with path depth and distance, since random variation partly averages out over many stages.
CCS
Composite Current Source
A cell timing model that stores the output current waveform rather than a single delay, giving more accurate results at advanced nodes than NLDM (Non-Linear Delay Model).
Clock skew
The difference in clock arrival time between two flip-flops. It adds to or subtracts from the time a path has, depending on its direction.
Critical path
The path with the least slack, which limits how fast the design can be clocked.
CRPR
Clock Reconvergence Pessimism Removal
Removing the pessimism added when the launch and capture clocks share part of the same clock path, since that shared part cannot be both fast and slow at once. Also called CPPR (Common Path Pessimism Removal).
Hold check
The requirement that data stay stable for some time after the clock edge. It fails when a path is too fast, and is fixed by adding delay.
Insertion delay
The time the clock takes to travel from its source to a flip-flop through the clock tree. It cancels between two flip-flops on the same tree but not on paths to ports or across clock domains.
Interface budget
The share of the clock period a block promises to whatever is on the other side of its ports, expressed as input and output delays in its constraints.
MCMM
Multi-Corner Multi-Mode
Analysing and optimizing a design across several process corners and operating modes at the same time, since each can have different critical paths.
Appears in: Static Timing Analysis
NLDM
Non-Linear Delay Model
A cell timing model that stores delay and output slew in tables indexed by input slew and output load.
OCV
On-Chip Variation
Differences in delay between devices on the same die caused by local variation in the process, voltage and temperature. Timing analysis models it by making some paths slower than nominal.
POCV
Parametric On-Chip Variation
A statistical form of OCV (On-Chip Variation) that gives each cell a delay distribution rather than a fixed derate, and combines the distributions along a path.
PVT
Process, Voltage, Temperature
The three conditions that set how fast a transistor switches. A corner is one combination of them, such as slow process, low voltage and high temperature.
Recovery check
The requirement that an asynchronous reset or set be released some time before the next clock edge, so the flip-flop leaves reset cleanly.
Setup check
The requirement that data arrive at a flip-flop some time before the capturing clock edge. It fails when the path is too slow.
Slack
The margin by which a path meets its timing requirement: required time minus arrival time. Positive slack passes; negative slack fails by that amount.
Smallest period
The shortest clock period at which a finished design would meet setup on its register-to-register paths. It depends on how hard the tools were pushed, so it moves when the requested clock does.
Appears in: Timing reports flash cardsYour move
SSTA
Statistical Static Timing Analysis
A form of STA (Static Timing Analysis) that propagates delay distributions instead of single values, reporting the probability that a path meets timing.
Appears in: Static Timing Analysis
STA
Static Timing Analysis
Checking every timing path in a design against its constraints by adding up cell and wire delays, without simulating any input patterns.
TNS
Total Negative Slack
The sum of the negative slack over every failing endpoint. Where WNS (Worst Negative Slack) gives the depth of the worst failure, TNS gives the size of the problem.
Appears in: Static Timing AnalysisTiming reports flash cards
WNS
Worst Negative Slack
The slack of the single worst failing path. Many tools report it as zero when nothing fails, so the margin of a passing design is read from the worst slack instead.
Appears in: Static Timing AnalysisTiming reports flash cards
Floorplan, placement and routing
Where things go on the die, and how they are connected.
Cell row and site
Standard cells are placed in horizontal rows of fixed height, and each row is divided into sites of the minimum cell width. Every cell must start on a site.
Congestion
Routing demand in a region approaching or exceeding the tracks available there. Overflow is demand beyond capacity, which the router must resolve by detouring.
Core and die
The die is the whole piece of silicon; the core is the area inside it where cells may be placed, surrounded by a margin for pins and power rings.
Detailed routing
Drawing the exact wire and via shapes for every net on legal tracks, then iterating to remove design-rule violations.
Filler cell
A cell with no logic, inserted into the gaps between placed cells to keep the supply rails and the wells continuous along each row.
Gate cloning
Duplicating a gate so that its load is split between two drivers, speeding up the nets it drives at the cost of area.
Global routing
Dividing the die into tiles and assigning each net a path through them, balancing demand against each tile's capacity. It produces a plan, not shapes.
Halo
A keep-out margin around a macro in which no standard cell may be placed, leaving room for routing to reach the macro's pins.
HPWL
Half-Perimeter Wire Length
Half the perimeter of the smallest rectangle enclosing a net's pins. It is a fast estimate of wire length used by placers.
Legalization
Moving cells from the positions global placement found onto legal sites in rows, without overlaps, while disturbing them as little as possible.
Metal layer
One of the stacked levels of wiring above the transistors. Lower layers are thin and fine-pitched for short connections; upper layers are thick and wide for long nets and power.
NDR
Non-Default Rule
A routing rule for specific nets, usually clocks, that uses wider wires or extra spacing to reduce resistance and coupling.
Pin access
Reaching a cell's pins from the routing grid without violating the rules. At small geometries it is often what limits routability.
Pin swapping
Exchanging the inputs of a gate whose inputs are logically equivalent, so that the latest signal uses the faster input. It costs no area.
Preferred direction
The direction, horizontal or vertical, that wires run on a given metal layer. Adjacent layers alternate, so a wire changes layer to turn a corner.
RSMT
Rectilinear Steiner Minimal Tree
The shortest tree of horizontal and vertical segments connecting a set of points, allowed to branch at extra points. Routers use it as the target shape for a net.
Appears in: Rectilinear Steiner Trees and FLUTE
RUDY
Rectangular Uniform wire DensitY
A quick congestion estimate that spreads each net's expected wire evenly over its bounding box and sums the result across the die.
Appears in: Machine Learning in Routing
Tap cell
A cell placed at regular intervals along each row to tie the wells and substrate to the supply, preventing latch-up.
Timing repair
Changes the tools make after placement to fix timing: resizing cells, inserting buffers, cloning gates and swapping pins.
Utilization
The fraction of the core area occupied by cells. A target set at floorplanning sizes the core; repair then adds cells, so the finished figure is usually higher than the target.
Via
A vertical connection between two adjacent metal layers.
Power
How the supply reaches every cell, and what it costs when it does not.
Dynamic power
Power spent charging and discharging capacitance when signals switch. It scales with frequency, capacitance and the square of the supply.
Ground bounce
The rise of the ground net above zero volts under a cell, the mirror of supply drop. A cell caught by both loses voltage from both ends.
Appears in: Your moveRead the die
IR drop
current times resistance drop
The fall in supply voltage between the power pads and a cell, caused by current flowing through the resistance of the power grid. Reported as a percentage of the supply.
Leakage power
Power drawn by transistors that are nominally off. It depends on the threshold voltage and temperature, not on activity.
Appears in: Timing reports flash cards
PDN
Power Distribution Network
The grid of rings, straps, rails and vias that carries the supply and ground to every cell.
Power strap
A wide supply or ground wire on an upper metal layer, repeated at a fixed pitch across the core and connected down to the rails.
Appears in: Sign-off checks and violations flash cards
Supply rail
The supply and ground wires that run along the top and bottom of every cell row, usually on the lowest metal layer.
UPF
Unified Power Format
A standard file format describing a design's power intent: its voltage domains, which blocks can be switched off, and the isolation and level shifters between them.
Appears in: OpenROAD flow commands flash cards
Sign-off and manufacturing
The checks a layout has to pass, and the processing it will go through.
Antenna effect
Charge collected on a long metal wire during manufacture that can damage the gate it connects to before the rest of the circuit exists to drain it. It is fixed with diodes or by breaking the wire across layers.
BEOL
Back End Of Line
The manufacturing steps that build the metal layers and vias above the transistors.
CMP
Chemical-Mechanical Polishing
The process that flattens each layer after deposition. It is why metal density must stay within limits across the die.
DFM
Design For Manufacturability
Design practices and checks that improve yield beyond the minimum rules, such as doubling vias and spreading wires.
DRC
Design Rule Check
Checking the layout against the foundry's geometric rules: minimum widths, spacings, enclosures and densities. A violation is a shape the foundry cannot reliably make.
ERC
Electrical Rule Check
Checking for electrically wrong connections such as floating inputs or outputs driving each other.
FEOL
Front End Of Line
The manufacturing steps that build the transistors themselves, before any metal.
LVS
Layout Versus Schematic
Extracting the circuit from the layout and comparing it with the netlist, to confirm the layout implements what was designed.
Parasitic extraction
Computing the resistance and capacitance of every wire from the layout, so that timing and power can be analysed with real interconnect.
Files and formats
The files a design travels in between tools.
CDL
Circuit Description Language
A SPICE (Simulation Program with Integrated Circuit Emphasis) style netlist format used as the reference circuit in LVS (Layout Versus Schematic).
DEF
Design Exchange Format
A text format describing a specific design's layout: the die, rows, placed components and routed nets.
GDSII
Graphic Design System II
The binary format in which the final layout is delivered to the foundry: every shape on every layer.
LEF
Library Exchange Format
A text format describing the physical view of cells and macros, their size, pins and blockages, and the routing layers of the technology. It carries no timing.
Liberty
The standard text format for cell timing and power: delay and slew tables, pin capacitances, and timing checks for each cell at one corner.
OASIS
Open Artwork System Interchange Standard
A more compact successor to GDSII (Graphic Design System II) for layout data.
SDC
Synopsys Design Constraints
The command format that states a design's timing intent: its clocks, input and output delays, and the paths that are exceptions.
SDF
Standard Delay Format
A text format carrying computed cell and wire delays, used to annotate timing onto a gate-level simulation.
SPEF
Standard Parasitic Exchange Format
A text format carrying the resistance and capacitance of every net, written by parasitic extraction and read by timing analysis.
SPICE
Simulation Program with Integrated Circuit Emphasis
The circuit simulator family, and its netlist format, used to simulate transistors and wires at the level of voltages and currents.
TCL
Tool Command Language
The scripting language most physical design tools are driven with, including OpenROAD.
Devices and processes
The transistors underneath, and the technologies they are made in.
ASAP7
Arizona State University 7 nanometre predictive process design kit
An open, predictive PDK (Process Design Kit) for a 7 nanometre FinFET (Fin Field-Effect Transistor) process, built for research and teaching rather than manufacture.
CFET
Complementary Field-Effect Transistor
A proposed transistor structure that stacks the n-type and p-type devices on top of each other to shrink cell area.
Appears in: Planar, FinFET, Gate-All-Around
CMOS
Complementary Metal-Oxide-Semiconductor
The logic style built from pairs of n-type and p-type transistors, so that a gate draws current mainly when it switches.
CPP
Contacted Poly Pitch
The spacing between neighbouring transistor gates. With the metal pitch, it sets how small a standard cell can be.
Appears in: What a Node Name Means
EUV
Extreme Ultraviolet
Lithography at a 13.5 nanometre wavelength, which prints the finest layers at advanced nodes in a single exposure.
FinFET
Fin Field-Effect Transistor
A transistor whose channel is a vertical fin wrapped by the gate on three sides, giving better control than a flat channel at small sizes.
LELE
Litho-Etch-Litho-Etch
Double patterning by splitting a layer between two masks, each printed and etched in turn.
MOSFET
Metal-Oxide-Semiconductor Field-Effect Transistor
The transistor digital chips are built from: a gate voltage controls the current between source and drain.
Appears in: Planar, FinFET, Gate-All-Around
Nangate45
An open 45 nanometre standard-cell library, widely used for research and as a teaching platform in the open flow.
OPC
Optical Proximity Correction
Deliberately distorting mask shapes so that, after optical effects, the printed shapes match the intended ones.
SADP
Self-Aligned Double Patterning
A technique that halves the pitch a lithography step can print by forming spacers on both sides of a printed line.
SKY130
SkyWater 130 nanometre
An open PDK (Process Design Kit) for a real, manufacturable 130 nanometre process, released by SkyWater with Google in 2020.
Threshold voltage
The gate voltage at which a transistor turns on. Low-threshold cells are faster and leak more; high-threshold cells are slower and leak less.
Tools and methods
The open tools the site is built on, and the algorithms named on its pages.
ABC
And-Inverter-Graph optimizer
The logic optimization and technology mapping engine inside Yosys, which represents logic as a graph of AND gates and inverters.
FLUTE
Fast Lookup Table Estimation
A method that builds a near-optimal RSMT (Rectilinear Steiner Minimal Tree) for small nets from precomputed tables, used inside global routers.
ILP
Integer Linear Programming
Optimization over variables restricted to integers, with a linear objective and linear constraints. Exact but expensive, so used on small subproblems.
KLayout
An open-source layout viewer and editor, also used to run design-rule checks in the open flow.
Maze routing
Finding a path for a net by expanding a wavefront across a grid from the source until it reaches the target, as in Lee's algorithm. It always finds a path if one exists, at a high cost in memory and time.
OpenROAD
An open-source tool that performs floorplanning, placement, clock tree synthesis, routing and analysis in one application, driven by TCL (Tool Command Language).
ORFS
OpenROAD-flow-scripts
The reference flow around OpenROAD: makefiles, scripts and platform configurations that take a design from RTL (Register Transfer Level) to layout. Every run behind the drills on this site used it.
Yosys
The open-source logic synthesis tool the open flow uses to turn Verilog into a netlist.
No term matches that search.