Learn chip physical design by doing
Complete the design challenge, solve graded problems, drill the tools, and take a real processor from netlist to finished layout right here in your browser. Everything is built from real runs of the open-source OpenROAD flow.
Chipbase Competition 01: Systolic Array AI Accelerator
Harden the full Gemmini design, an open-source AI accelerator, from RTL (Register Transfer Level) to GDSII (Graphic Design System II) with open tools. Entries are scored on clock speed, area and power.
See the challengeTake a real processor through the flow
riscv32i, a small RISC-V (Reduced Instruction Set Computer, fifth generation) processor: 8,636 cells and four memories. Set it up, press Run, and watch the whole flow in a few seconds.
A simplified engine in your browser, not OpenROAD, on the design's real netlist and library. The real run used the flow's settings (1,138 ps, 62% full). How the engine works
Your run in three dimensions
The chip your run made, as it would stand in silicon: the cells on the bottom, then each metal layer of routed wire above the one before, joined by vias. Drag to turn it, and switch layers on and off.
riscv32i at the flow's own settings, as the engine draws it. Press Run, and the chip you make replaces it here, ready to turn, zoom and take apart layer by layer.
Problems
Small tasks graded like a judge, some by a real OpenROAD run on a real netlist.
Sandboxes
One real block walked through every stage of the flow, and whole designs to take through it yourself, in your browser.
- The OpenROAD flow walkthrough7 stages
- riscv32idesign
- aesdesign
- gcddesign
Games
Fast drills on the knowledge around the problems, every question built from a real run.
- Command flash cards767 cards in 10 decks
- Log forensics41 cases in 9 stages
- Call the number41 summaries in 5 families
- Your move20 situations in 7 kinds
Education
One page per topic, covering what a physical design engineer needs to know about it.
- Logic Synthesis6 sections
- Static Timing Analysis14 sections
- Floorplanning11 sections
- Placement12 sections
- Clock Tree Synthesis11 sections
- Routing11 sections
Methods and algorithms
The classic algorithms behind every flow stage: what each does, where it came from, and where it is used.
- Synthesis5 pages
- Floorplanning21 pages
- Placement19 pages
- Clock Tree Synthesis8 pages
- Routing24 pages
- Timing Analysis8 pages
Foundry processes
What sits underneath the flow: process design kits, cell libraries, metal stacks, variation.
- Process design kits3 pages
- Devices2 pages
- Interconnect2 pages
- Lithography2 pages
- Sign-off3 pages
- Open process design kits2 pages
Glossary
Every term and acronym the site uses, defined once and linked to the pages that use it.
- The flow17
- Timing21
- Floorplan, placement and routing21
- Power8
- Sign-off and manufacturing9
- Files and formats11
Stuck on a passage? Ask your own model
Highlight any sentence on the site and copy it as a reference. Paste it into Claude, or any assistant that speaks MCP (Model Context Protocol), and the free Chipbase tutor looks up the page you were reading, so the explanation starts from exactly where you got stuck. It runs on your machine, with the model you already use.
Get the tutor- Highlight
- Copy
- Paste and ask
- Tutor looks up
A flip-flop captures its data input only if that input is stable across a small window around the clock edge: the setup time before the edge and the hold time after it. On a path from a launch flip-flop through logic to a capture flip-flop, those two library numbers become two checks.
hold slack = arrivalmin − thold
The asymmetry drives everything downstream. Setup is the late check: it uses the maximum path delay and measures data against the next clock edge, so a longer period buys margin. Hold is the early check: it uses the minimum path delay and measures data against the same edge, so the period cancels and no clock setting can fix a hold violation.
Copy reference> (Chipbase: Static Timing Analysis > Setup and hold: the two checks)
hold slack = arrivalmin − thold
arrivalmin: earliest data arrival, from the fastest path