Time borrowing (latches)

Time borrowing with transparent latches. The circuit is a chain of combinational-logic stages between sequential elements, ending in a capture flip-flop. An edge-triggered flip-flop has a hard deadline at the clock edge: a stage slower than one period fails, and a fast stage's early slack is wasted.

A level-sensitive latch is transparent for a fixed window W after the edge (the clock high phase, shown in green). Data arriving late flows straight through, so the stage feeding a latch can borrow time past the edge - repaid because the next stage then starts that much later.

• Click a sequential element to switch it between flip-flop and latch. Under each logic cloud, a gauge shows that stage against its clock edge and the latch's transparent window.
• Put a latch only where a stage overruns its edge (so the overrun can borrow). Leave the rest as flip-flops: a latch adds hold / min-delay race risk, so using one where the stage already fits is a needless cost.
• The endpoint is a fixed flip-flop, and it works out because the average stage delay fits the period even though some stages do not.

Find the fewest latches that let every stage be captured, then Submit design. Over-latching (a latch where a flip-flop would do) is marked wrong.