Clock Tree Synthesis

What clock tree synthesis is

Clock tree synthesis builds the network that carries the clock from its source to the clock pin of every flip-flop. Placement leaves the clock as a single ideal net; clock tree synthesis replaces it with a real, buffered tree that reaches thousands of sinks. Its goal is to make the clock arrive at every flip-flop at nearly the same time, because the spread in arrival, the skew, is subtracted directly from the timing budget of every path.

Skew, latency, and insertion delay

Three numbers describe a clock tree:

• Skew is the difference in clock arrival time between two flip-flops. Low skew is the primary goal, because skew eats setup and hold margin.
• Latency, or insertion delay, is the delay from the source to a flip-flop. It is the price of driving the tree, and it is kept as equal as possible across sinks.
• Transition (slew) at each clock pin must stay sharp, or the flip-flops see a slow, uncertain edge.

Skew and latency trade off: a deeper, more buffered tree can balance skew tightly but adds latency, and latency itself interacts with variation, so the two are optimized together.

Balancing from the source

The simplest clock network is a star: one driver at the source wired straight to every flip-flop. Balancing it means positioning that source so its distances to the sinks are as even as possible. But a star has an irreducible skew floor, because the sinks sit at different distances and one driver cannot equalize them, and a single gate cannot drive thousands of loads in any case. That floor is exactly why real clocks are built as buffered trees, which the rest of this page develops.

The H-tree and balanced trees

The cleanest way to reach many sinks at equal delay is geometric symmetry. An H-tree places the source at the center and branches in nested H shapes so that every root-to-leaf path is the same length, and therefore the same delay. An X-tree is its diagonal cousin: its branches run at 45 degrees, so each leaf's distance is the straight-line (Euclidean) distance rather than the longer right-angle path, which gives shorter, lower-latency balanced routes where diagonal routing is allowed. Real designs are not perfectly regular, so production tools build balanced trees by clustering sinks and equalizing path delays rather than drawing a literal H, but the H-tree is the ideal the balancing chases. The figure builds one.

Clock buffers and inverter pairs

No single gate can drive thousands of far loads, so the tree is buffered at every level. Clock buffers (often balanced inverter pairs) restore drive strength and keep the edge sharp, and their delays are what the tool tunes to equalize path latency. Because the clock switches every cycle, these buffers are a large share of a chip's dynamic power, which is why clock networks are designed with as few buffers as the skew target allows.

Tree topologies and clustering

A production clock tree is grown by clustering: nearby sinks are grouped, each cluster is driven by a buffer, the buffers are themselves clustered, and the process repeats up to the source. The tool balances the delay from each buffer to its sinks at every level. This clustering is what lets an irregular sink distribution still reach low skew, where a rigid H-tree could not.

Clustering can grow into several shapes, each trading skew, power, and tolerance to variation:

A mesh is chosen where skew must be tiny and the power budget allows it, a tree where power matters more, and a spine where the sinks line up in rows.

Useful skew

Zero skew is not always the best target. Deliberately delaying the capture clock of a tight path buys it setup time, and deliberately advancing it relaxes a hold-critical path. This useful skew, or clock skew scheduling, spends the clock arrival times as an optimization variable, borrowing time from paths with margin to give to paths without it. It must be applied carefully, because the same shift that helps setup hurts hold.

Clock power and multiple clocks

Because the clock switches every cycle, it is one of the largest power consumers on a chip, and two techniques cut that power. Most designs gate the clock, switching it off to idle blocks with clock-gating cells; clock tree synthesis must build the tree through these gates and check that the enable timing never lets a partial clock pulse through. The second lever is multi-bit flip-flop banking: several single-bit flip-flops that share a clock are merged into one multi-bit cell with a single shared clock input, so the tree drives one clock load instead of many, cutting buffers and power. Banking only works for flip-flops close enough to merge without hurting their data timing, so it is done with placement in view.

Designs with several clocks, or with generated and divided clocks, need a tree per clock and careful handling where the domains meet.

Non-default-rule clock routing

The clock is not routed with ordinary signal wires. Its trunks use non-default rules: they are widened, because a wide, low-resistance wire carries the sharp edge the flip-flops need and eases electromigration on a net that switches every cycle, and they are given extra spacing or grounded shield wires on each side so neighbouring signals cannot couple noise onto the clock and jitter it. This spends routing-track budget, since a wide, shielded trunk takes the room of several ordinary tracks, so it is spent on the clock, where a clean and quiet edge matters most.

Variation on the clock

Because the clock path feeds both the launch and capture side of every check, variation on it matters twice. On-chip variation is applied to clock paths, and common-path pessimism removal credits back the shared part of the launch and capture routes. Clock jitter from the source and duty-cycle distortion in the tree are budgeted as uncertainty. A clock tree is signed off across the same corners as the data paths.

A structural defence against variation is to give every source-to-sink path the same number of buffer stages. When two paths pass through the same count of similar buffers, a process or voltage shift speeds or slows both together, so most of the variation is common to them and cancels in the skew between them. A tree with unequal depth to different sinks loses that cancellation, so a variation-tolerant clock balances buffer levels, not only total delay.

Where clock tree synthesis sits in the flow

Clock tree synthesis runs after placement and before, or interleaved with, routing, because it must know where the flip-flops are but its buffers change placement and timing. After it, the clock is propagated rather than ideal, hold violations become real and must be fixed, and the design carries the insertion delay and skew that the rest of sign-off accounts for.