Hold fixing (delay insertion)

Hold fixing. A hold check compares data launched by one clock edge against the same capture edge: the newly launched value must not race through the logic and reach the capture flip-flop before that flop has safely held its previous value. Here the capture clock arrives later than the launch clock (positive clock skew), so the data gets there too early and the path misses hold.

The fix is to slow the data path down by inserting delay cells. But the same path is still checked for setup against the next edge, so adding too much delay makes the data arrive too late and breaks setup instead. The path delay must land inside a window: at least the hold floor, at most the setup ceiling.

Click a slot on the data path to add or remove a delay cell. Watch the path-delay marker move between the hold floor and the setup ceiling, land it inside the green window, and use the fewest cells that pass both (less added area and power, and more setup margin left over). Then Submit fix.