Floating nodes and tie cells

Floating nodes and tie cells. ERC (Electrical Rule Check) flags every gate input that is not properly driven, but the correct fix depends on what the input is. Each flagged pin gets one of four dispositions:

• Leave it if the input is already driven by a real net. Tying a driven input makes the tie cell fight the driver, a contention short.
• Tie-high or tie-low a floating control input that must hold a constant: high for a logic 1, low for a logic 0. A constant does not go straight to a rail; it goes through a tie cell (which protects the gate oxide).
• Route a net to a floating data input. A dangling data pin is a real open (a missing connection). It must be wired to its signal; tying it off would only hide the bug.

The slice is drawn with real cell symbols (NAND, AND, OR, inverter, and a flip-flop with an unused async reset). Click a flagged pin to cycle its disposition, using the netlist on the right to read each pin's role, then Submit fixes.