Physical design you can touch. Start with the OpenROAD flow walkthrough, one real block taken through every stage step by step, then open a sandbox and make the calls yourself. No installs, no accounts: everything runs live in your browser.
One design, taken from Verilog to finished layout through the open-source OpenROAD flow, stage by stage, with every choice made and explained.
Where every other example starts. Read the source, turn the always blocks into logic, choose how the adders carry, map the registers and then the logic onto real cells, and write out the netlist the floorplan example opens on its first step. Watch the cell count climb before it falls.
Every step a physical design engineer takes on one small block, in order: read the design in, size the die, make rows and tracks, place the pins and the memories, add halos, build the power grid, insert the tap cells, forecast the congestion, and write the floorplan out. Real commands, one fixed design, and what to check at every step.
The same block, picked up from the floorplan it just left: prepare the netlist, spread every cell with the analytic placer, buffer the long wires, then snap it all onto rows with as little movement as possible. Watch the density map fill in and the peak bin come back under the line.
The same block again, now with a real clock. Group the flip-flops, branch out from the clock port until every group is reached equally, and watch the tree build itself level by level. Then measure what it cost: insertion delay, skew, and the hold violations that only appear once the clock stops being ideal.
The same block, now drawn in metal. Find where a via may land on every pin, give each net a corridor and watch the congestion clear, repair timing against the corridors, fix the antennas that could destroy a gate in the factory, then turn it all into exact shapes on exact tracks until no design rule is broken.
The same block, finished and measured. Extract the parasitics from the metal that was actually drawn, find out what that did to the clock, then walk the worst path gate by gate and ask the only question that matters: did the data arrive before it was required? Setup, hold, and the whole design at once.
The same block, taken from signed off to taped out. Fill the empty metal and find out what that did to the timing, solve the power grid for how far the supply sags, stream the real layout of every cell into one file, then run the rule deck on every polygon and prove, transistor by transistor, that the layout is the netlist.
Whole designs you take through the flow yourself: pick the settings, and see the layout, timing, area and power that come out.
A small, real processor for the RISC-V (Reduced Instruction Set Computer, fifth generation) instruction set, taken through the whole OpenROAD flow with settings you choose, and the result laid out in front of you: the layout, the timing, the area, the power.
An AES (Advanced Encryption Standard) encryption core: about fourteen thousand cells of dense logic and no memories, where congestion and power, not memories, shape the layout.
The smallest whole design: a unit that finds the greatest common divisor of two numbers, a few hundred cells in all. Small enough to see every cell and every wire, and the design the OpenROAD flow uses to check itself.