Clock gating insertion

Clock gating. The clock network toggles every cycle and burns a large share of a chip's dynamic power, including in registers that are not doing useful work that cycle. A clock-gating cell (an ICG, Integrated Clock Gating cell) fixes that: it watches a register bank's enable signal and, on the cycles the bank is idle, holds the bank's clock still so those flip-flops stop toggling and stop drawing switching power.

Each register bank below shows two numbers: its clock power (what it burns free-running) and its idle fraction (the share of cycles it sits idle). Gating a bank therefore saves idle fraction times clock power. Click a bank to gate it.

The catch is the cost. Every gating cell you add carries its own overhead (its leakage and area), charged once. Banks driven by the same enable signal form an enable domain (the columns), and all the banks in one domain share a single gating cell. So:

• Gating the first bank in a domain inserts its gating cell and pays the overhead once.
• Gating the other banks in that same domain is then free savings: no new cell.
• Opening a new domain just to gate a rarely-idle bank can cost more overhead than that bank saves.

Net power saved past target - net savings is everything the gated banks save, minus one overhead charge for each domain you gate. Gate the idle-heavy banks, sweep up the other banks in domains you have already opened, and leave the barely-idle lone banks free-running. Beat the target, then Submit design.