Synthesis
Where the netlist comes from. Read the register transfer level description, turn it into logic, and cover that logic with the cells this process actually has. Nothing physical is decided here, and yet the die size already is: the area every later stage divides up is whatever synthesis produced.
Floorplanning
The opening move of the backend. Carve the die into core and margins, shape the block, drop the macros, plan the power grid. Every later stage inherits its geometry from decisions made here, and a bad floorplan cannot be optimized away.
Placement
Millions of standard cells receive exact positions on the rows. Wirelength, timing, and routability are mostly decided here, long before a single wire exists: placement is where the flow's optimization muscle lives.
Clock Tree Synthesis
The clock must reach every flip-flop at almost the same instant. Build the buffer tree that distributes it, trading skew against insertion delay against power on the wire that toggles every single cycle.
Routing
Connect every pin of every net with real wires on the metal stack: dodge the macros, dodge each other, honor the design rules. Sixty years of algorithms about finding paths through a crowded grid.
Timing Analysis
The referee of the whole flow. Propagate arrival and required times through every path and prove the chip meets its clock, without simulating a single vector. Every stage above optimizes against its verdict.
Finishing
The last distance to a file a foundry can build. Fill the empty metal so the wafer polishes flat, swap every abstract for the cell's real polygons, then prove the result obeys every rule of the process and is still the circuit synthesis wrote.