Education

The library

One shelf for each physical design topic, and one book for each section of its reference page. Take a book down to open that section, or start a shelf from the beginning. Practise what you read in Problems, and go deeper into the methods under Methods and algorithms.

SHELF 01 Logic Synthesis From register transfer level code to a netlist of real library cells. 6 booksStart reading →
1 What logic synthesis is 2 Technology-independent optimization 3 Technology mapping
4 Sequential optimization 5 Datapath and operator selection 6 Where synthesis hands off
SHELF 02 Static Timing Analysis Proving every path meets the clock, and reading the reports that say so. 14 booksStart reading →
1 What static timing analysis is 2 The timing graph 3 Setup and hold: the two checks 4 Timing paths and path groups 5 Slack, WNS, and TNS
6 Delay calculation and library models 7 Clocks: latency, skew, jitter, and uncertainty 8 More sequential checks 9 Constraints (SDC): defining the problem 10 Corners and modes (MCMM)
11 On-chip variation and pessimism removal 12 Crosstalk and signal-integrity timing 13 Static timing in the flow and at sign-off 14 Reading a timing report
SHELF 03 Floorplanning The die, the macros, the power grid and the pins, before any cell is placed. 11 booksStart reading →
1 What floorplanning is 2 The inputs and the die 3 Aspect ratio and utilization 4 Macros and blocks
5 Partitioning 6 The power delivery network 7 Power domains and multi-voltage 8 Thermal-aware floorplanning
9 Input and output placement 10 Placement blockages and regions 11 Why the floorplan decides the flow
SHELF 04 Placement Putting every cell in its place: wirelength, density, legality and timing. 12 booksStart reading →
1 What placement is 2 Wirelength: the objective 3 Global placement 4 Legalization
5 Detailed placement 6 Density and congestion 7 Timing-driven placement 8 Clock-aware placement
9 Mixed-size placement 10 Filler and tap cells 11 Placement regions and constraints 12 Placement and the downstream flow
SHELF 05 Clock Tree Synthesis Delivering the clock to every flip-flop at nearly the same moment. 11 booksStart reading →
1 What clock tree synthesis is 2 Skew, latency, and insertion delay 3 Balancing from the source 4 The H-tree and balanced trees
5 Clock buffers and inverter pairs 6 Tree topologies and clustering 7 Useful skew 8 Clock power and multiple clocks
9 Non-default-rule clock routing 10 Variation on the clock 11 Where clock tree synthesis sits in the flow
SHELF 06 Routing Connecting every net with real metal, under every design rule. 11 booksStart reading →
1 What routing is 2 The routing grid, layers, and tracks 3 Global routing 4 Steiner trees and net topology
5 Track assignment 6 Maze routing 7 Detailed routing and design rules 8 Congestion, rip-up, and reroute
9 Timing-, crosstalk-, and manufacturing-aware routing 10 Antenna and via reliability 11 Where routing sits in the flow
SHELF 07 Physical Verification The last checks before tapeout: rules, connectivity, antennas and density. 9 booksStart reading →
1 What physical verification is 2 Design rule checking 3 Layout versus schematic 4 Antenna rules 5 Electrical rule checks
6 Density and metal fill 7 Lithography and manufacturability 8 Reliability sign-off 9 Sign-off and tapeout
SHELF 08 ECO (Engineering Change Order) Late, targeted fixes to a built design, disturbing as little as possible. 9 booksStart reading →
1 What an engineering change order is 2 The two kinds of ECO 3 Setup ECO: making a path faster 4 Hold ECO: adding delay 5 Clock ECO and useful skew
6 Electrical and design-rule ECO 7 Functional ECO and spare cells 8 Doing an ECO with minimal disturbance 9 Verifying an ECO