Problems /
Static Timing Analysis /
On-chip variation and CPPR
On-chip variation and CPPR
Static Timing Analysis
hard
interactive · in-browser
On-chip variation and CPPR. A launch flip-flop feeds combinational logic into a capture flip-flop. On-chip variation (OCV) derates the launch clock path late (slow, x dLate) and the capture clock path early (fast, x dEarly) so the analysis is pessimistic. Here it drives the path negative.
- Both clocks first travel a common trunk of buffers, then split to the two flip-flops. That shared trunk cannot be slow for launch and fast for capture at the same instant, so the derate difference on it is fake pessimism.
- Common-path pessimism removal (CPPR) credits it back. The credit is the shared wire delay times the derate spread: credit = (shared delay) x (dLate - dEarly). The divergent branches after the split are real skew and earn no credit.
Click the clock-tree segments that are shared by both flip-flops (the whole trunk from the source to the split), then Submit sign-off. Identify the full common path and no branch segment.