Gate sizing to close a setup path
Gate sizing (timing optimization). This is a real register-to-register timing path analyzed with static timing analysis (STA). Data leaves the launch flip-flop after its clock-to-Q delay, runs through a small combinational cone that splits and reconverges, and must reach the capture flip-flop with setup margin before the next clock edge. Each combinational gate has a drive-strength slider.
When you run timing, arrival times propagate forward along the arcs. Where paths reconverge, the arrival is the latest of the incoming arcs - that is the critical path. Required times propagate backward from the setup constraint, and the slack at each node is required minus arrival.
- Setup slack >= 0 - the data must arrive at the capture flip-flop no later than the clock period minus setup. The critical path (the least-slack chain, highlighted) is what fails first, so a gate left small on one branch can make that branch critical even when the other is fast.
- Area in budget - the total drive strength must stay under budget, so you cannot simply make every gate huge.
Two catches mirror logical-effort sizing. A gate driving a heavy load is slow, so the stages near the capture flip-flop want more drive. And a bigger gate has a bigger input capacitance that loads whatever drives it: sizing one gate up speeds its own arc but slows the arc feeding it.
Running timing prints a per-arc timing report for the critical path, like a
report_timing from a static-timing tool: each stage shows the cell and its
drive size, its output load (Cout), the signal slew (transition), the arc
delay, and the cumulative arrival, ending with the required time and the
slack. Read it to see exactly how a size change moves the numbers: upsizing a
gate drops that row's Cout ratio, so its slew and delay fall, while the row above
it gains load and its delay rises. The net effect on the endpoint arrival is what
you are steering.
Work the way the real flow does: adjust the drive strengths, then click Run timing to regenerate the report. The report, slack, and verdict update only when you run timing, and any later change marks them out of date until you run again. Once the slack is positive, Submit design.