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Logic Synthesis /
Datapath operator selection
Datapath operator selection
Logic Synthesis
medium
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Datapath operator selection. An arithmetic operator like + is not one circuit. The same addition can be built three ways, and the lab draws each as its real gate-level structure so you can see the trade-off:
- ripple-carry: one row of full adders, the carry rippling from cell to cell. Small area, but the long carry path makes it slow.
- carry-select: two ripple rows (one assuming carry-in 0, one assuming 1) plus a mux that picks the right answer the moment the carry-in is known. About double the area, but faster.
- carry-lookahead: full adders plus a block that computes every carry in parallel. The most area, the shortest delay.
The datapath chains four adds, out = ((((v+w)+x)+y)+z), so the path delay is the sum of the four adders' delays. Click an adder to change its architecture. Meet the delay target at the least total area: making every adder fast is wasteful, so spend the fast architectures only where you must. Then Submit datapath.