ECO

What an engineering change order is

An engineering change order (ECO) is a small, targeted change applied to a design that is already implemented, placed and routed and mostly closed, without re-running the whole flow. The change is made in place, disturbing as little of the existing layout as possible, and then the affected part is re-verified. Two situations call for it: a late need to close the last few timing or design-rule violations, and a late need to change the logic itself, to fix a bug or add a small feature, after the design is already built.

The reason to work this way, rather than editing the source and re-implementing, is that re-implementation throws away the placement, routing, and closure already achieved and can move violations somewhere new. An ECO preserves that work and touches only what must change. For a functional change there is a second reason: a change confined to the metal and via layers reuses the more expensive transistor masks, so the silicon revision is cheaper and faster.

The two kinds of ECO

A timing ECO must not change what the circuit computes; every move below leaves the logic function untouched. A functional ECO does change the logic, and so it carries an extra obligation: proving that the changed netlist matches the intended new function, with a logic equivalence check (LEC).

Setup ECO: making a path faster

When a register-to-register path arrives too late (a setup violation), the ECO speeds it up. The moves, from cheapest to most disruptive:

The two footprint-preserving moves, the threshold-voltage swap and the pin swap, are preferred first because they change no placement: a lower-Vt cell drops into the same site, and a pin swap changes only wiring. Upsizing and buffering add or grow cells and so need a little placement and routing. Every setup move trades against power (upsizing and lower Vt raise it) and against the hold checks, which it can newly violate, so the path is re-timed after the change.

The pin swap works because the inputs of a gate are logically interchangeable but not electrically equal. Inside a CMOS (Complementary Metal-Oxide-Semiconductor) gate the inputs drive a series stack of transistors between the output node and the supply rail. In a NAND (Not-AND) gate that stack is the NMOS (n-type Metal-Oxide-Semiconductor) pull-down path from the output down to GND (ground). The input that switches the transistor nearest the output is fast: the lower transistors turned on earlier and already pulled the internal stack nodes down, so the last transition only has to move the small output node. The input that switches the transistor nearest the rail is slow: it must discharge the whole stack at the last moment. The pin-to-output delay therefore depends on stack position, so the tool assigns the latest-arriving signal to the pin closest to the output and pushes the earlier signals onto the slower pins.

Logic restructuring is the deepest of these moves, because it changes the shape of the logic rather than just the cells. A path can be slow simply because it runs through too many gates in series, and a late-arriving signal buried deep in that chain then passes through every one of them. Restructuring rebuilds the same function as a shallower, more balanced tree, and puts the latest-arriving signal nearest the output so it sees the fewest gates after it. It closes timing with no change in what the logic computes, but it disturbs more of the netlist than the local moves above, so it is reached for when those are not enough.

Hold ECO: adding delay

A hold violation means data reaches the capture flip-flop too early, before the clock edge has safely latched the previous value. Unlike setup, the fix is to make the path slower, by inserting delay cells or buffers on the fast path until the earliest arrival clears the hold requirement.

• earliest data arrival the fastest a signal can reach the capture flip-flop
• hold requirement the time after the clock edge the input must stay stable

Hold is fixed late, after routing, because it depends on the real clock and wire delays that only exist once the clock tree and routes are built. The delay must be added without pushing the same path or a neighbour into a setup violation, so hold-fixing cells are placed where there is slack to spare, and the path is checked against both setup and hold afterward. Because hold cells are numerous and small, they are a large share of late ECO activity.

Clock ECO and useful skew

Instead of changing the data path, an ECO can shift a flip-flop's clock arrival. Delaying the capture clock gives a late path more time (helping setup) at the expense of the next stage; advancing it does the reverse. Moving slack between adjacent stages this way is called useful skew, and as a late change it is done by editing the clock tree near that flip-flop.

Electrical and design-rule ECO

Some late violations are electrical rather than path timing. A net that switches too slowly (a maximum-transition violation), drives too much capacitance (a maximum-capacitance violation), or fans out to too many loads (a maximum-fanout violation) is fixed with the same buffering, driver-cloning, and upsizing moves, splitting the load so no driver is overloaded. An antenna violation found late is fixed by adding a protection diode or jumping the route to another layer. These are ECOs in the same sense: local, in-place, re-verified.

Functional ECO and spare cells

A functional ECO changes the logic after the design is built. The difficulty is that the base transistor layers are already committed, so there is nowhere to put new gates unless they were provided in advance. They are: designers scatter spare cells, unused gates and flip-flops, across the layout before tapeout exactly so a later change has something to use.

A metal-only ECO implements the logic change by rewiring these spare cells, changing only the metal and via masks. The transistor masks are untouched, so the revision needs only a few new masks and a short turnaround. It works only when the change can be built from the spare cells that happen to be nearby and of the right type.

When the change is too large or the right spares are not close enough, the ECO must add real cells, which requires new base layers: an all-layer ECO, a full mask set and a long, expensive turnaround. Part of doing a functional ECO is deciding which case applies.

Doing an ECO with minimal disturbance

Whichever move is used, the point of an ECO is to change little. The affected region is opened for edits and the rest of the block is frozen (marked don't-touch), so the existing placement and routing stay intact. The changed nets are rerouted on spare tracks with as little rip-up as possible.

Any cell an ECO inserts still has to be legalized: snapped onto a legal site on the placement grid, in a standard-cell row, without overlapping the cells already there. The placer first drops the new cell at its ideal spot, where timing and wirelength want it, but that spot is usually already occupied, so legalization moves the cell to the nearest free, on-grid gap. It moves each cell as little as possible, because displacement from the ideal spot erodes the very timing the ECO was trying to fix, and on a packed die the nearest legal gap is often in an adjacent row. A large or scattered change defeats the purpose, so ECOs are kept small and are often batched so one revision carries several fixes.

Verifying an ECO

An ECO is not done when the edit is made; it is done when the change is proven not to have broken anything.

• Timing: re-run static timing analysis (STA) on the changed paths, checking both setup and hold, since a setup fix can create a hold problem and a hold fix can create a setup problem.
• Physical: re-run the design-rule check (DRC) and the layout-versus-schematic check (LVS) on the changed region, because new cells and routes can break spacing or connectivity.
• Function: for a functional ECO, run a logic equivalence check (LEC) to prove the edited netlist implements exactly the intended change and nothing else.

Only when the changed region passes these, with the rest of the block untouched, is the ECO signed off.