Prove that a billion paths meet the clock without simulating a single vector. One graph algorithm at the core, wrapped in delay models, pessimism control, statistics, and the optimization loops that spend its slack reports.
Static timing is a longest-path computation on a directed acyclic graph plus a delay model for its edges. These two pages are the foundation.
Levelize the circuit graph, push worst-case arrival times forward and required times backward; slack at every node falls out. Covers every path implicitly, no vectors needed.
Delay to a node in an RC (Resistance-Capacitance) tree: sum over resistances on the path, each times all the capacitance downstream of it. Crude, robust, and the estimator inside forty years of layout algorithms.
Past the first micron, wires are circuits. Reducing extracted RC (Resistance-Capacitance) networks to usable delays is its own algorithmic field.
Corner-based worst-casing lies in both directions. These methods remove provably impossible pessimism and model variation statistically.
When launch and capture clocks share tree segments, worst-casing one early and one late double-counts variation the shared wire cannot exhibit; credit it back, exactly.
Propagate delay distributions instead of corner numbers: arrival times become random variables, slack becomes a yield curve. Canonical first-order forms made it tractable; adoption stayed selective.
Analysis is only half the loop: these algorithms spend area and power to buy back slack, guided by the timer's own gradients.
Given a routed net and legal buffer positions, choose where to insert buffers to maximize required time at the driver: solved exactly, bottom-up, by propagating (capacitance, required-time) candidates and pruning the dominated ones.
Choose each gate's drive strength: logical effort gives the closed-form theory (equalize effort per stage), convex and Lagrangian formulations give the optimizer, and library reality makes it discrete.
Move registers across combinational logic without changing function: minimum feasible clock period reduces to shortest-path feasibility, solved exactly on the circuit graph.