Technology mapping for area

Technology mapping for area. After the logic is simplified, it must be built from real standard-cell library gates. Mapping covers the technology-independent network with library cells so that every node is covered exactly once, at the least total area.

The subject graph is a real network of primitive gates: g1 = AND(a,b), g2 = AND(g1,c), g3 = OR(g2,d), g4 = INV(g3) = out. Each library cell matches a real pattern of these gates: AND3 is the two chained ANDs, NOR2 is the OR feeding the inverter, AOI21 is the AND-OR-INV run, and the small cells cover one gate each.

A cell that spans several gates is usually cheaper per gate, but the biggest match is not always best: grabbing the AOI21 covers three gates cheaply yet leaves g1 stranded as its own AND2, and that total loses to covering the two ANDs as one AND3 and the OR-INV as one NOR2. The least-area cover is a balance.

Click cells to build a valid cover (every gate covered exactly once, none covered twice), reach the minimum area, then Submit mapping.