Challenge

Learn ▾

Education ▸

All topics Logic Synthesis Static Timing Analysis Floorplanning Placement Clock Tree Synthesis Routing Physical Verification ECO

Methods & Algorithms ▸

All stages Synthesis Floorplanning Placement Clock Tree Synthesis Routing Timing Analysis Finishing

Practice ▾

Problems ▸

All problems Logic Synthesis Static Timing Analysis Floorplanning Placement Clock Tree Synthesis Routing Physical Verification ECO

Games ▸

All games Command flash cards Log forensics Call the number Your move Read the die

Sandboxes ▾

The OpenROAD flow walkthrough ▸

1 · Synthesis 2 · Floorplanning 3 · Placement 4 · Clock tree synthesis 5 · Routing 6 · Timing sign-off 7 · Finishing and tapeout

Designs you can do in the browser ▸

riscv32i aes gcd

Reference ▾

Glossary Foundry Processes Open data: the OpenROAD runs

github.com/Samcooper01

linkedin.com/in/sam-cooper12

Sandboxes / Designs you can do in the browser / aes

aes

aes, an encryption core for the Advanced Encryption Standard, dense with logic and with no memories, taken through the OpenROAD flow with settings you choose.

Chipbase

Learn chip physical design by doing: complete the design challenge, solve graded problems, drill the tools, and take a real processor from netlist to finished layout in your browser, all built from real runs of the open-source OpenROAD flow.

Try it yourself

Challenge Problems Games Sandboxes Harden a chip in your browser

Learn

Education Methods and algorithms Foundry processes Glossary

Help and records

Tutor Your progress Open data

Built on

OpenROAD Yosys KLayout ASAP7 Chipyard Gemmini