Pin placement

A DDR memory-controller PHY block. The internal macros are placed and locked (hatched): four data byte lanes (lane0-lane3), the clock pll, the command/address block ca_blk, and the controller ctl. Your job is the block's I/O pins: drag each boundary pin to the die edge nearest the macro it serves so its wire stays short. All ten pins start bunched on the top edge, which is wrong for most of them.

• Timing closed - each high-speed net (bold) under budget. A data pin belongs beside its lane (dq0 to lane0, dq1 to lane1, dq2 to lane2, dq3 to lane3), the clock ck by the pll, and ca by the command/address block. Put each pin on the boundary closest to its block.
• Legality - every pin stays on the die edge and keeps a pitch from its neighbours. Where pins share an edge (rst/cke by the controller, dq2/zq by lane2), spread them apart.
• No congestion overflow - pins crowded on one side make their wires fan across the die and pile up. Moving each to its own edge relieves it.

Drag the pins, Run analysis, Place & Route, Submit.