Education / Routing

Routing

Connecting every net with real metal on the layer grid: global routing, Steiner topology, track assignment, detailed routing, and the rules that make it hard.

What routing is

Routing connects the pins of every net with actual metal, turning a placed netlist into a fully wired layout. It runs on the fixed grid of metal layers the process provides, and it must connect every net while obeying thousands of design rules and avoiding shorts. On a large block it is the most time-consuming stage of the flow, and it is split into global routing, which plans, and detailed routing, which draws.

The routing grid, layers, and tracks

Routing happens on a stack of metal layers, alternating preferred directions (one layer horizontal, the next vertical), connected by vias. Each layer has a track pitch set by lithography. Lower layers are thin, dense, and resistive, used for short local connections; upper layers are thick and fast, used for long wires, the clock, and power. But the thick upper layers have a wider pitch, so they carry far fewer tracks than the dense lower layers. Those fast tracks are scarce, which is why the router cannot simply put every net up high: layer assignment spends the fast upper tracks on the long and timing-critical nets and leaves short local nets on the lower layers.

Global routing

Global routing plans each net's route coarsely, assigning it to a sequence of routing regions (tiles) without drawing exact wires. It builds a congestion map of supply and demand per tile and spreads nets to keep any tile from overflowing its track capacity. Modern global routers use negotiated-congestion routing: nets rip up and reroute repeatedly, paying a rising cost for crowded tiles until the congestion resolves. The figure runs that negotiation.

Steiner trees and net topology

A multi-pin net is not a single wire but a tree, and the shortest tree connecting a set of pins is a rectilinear Steiner tree, which may add branch points beyond the pins. Routers build a low-cost Steiner topology for each net first, then route its two-pin segments. A good topology decides most of a net's wirelength before any detailed wire is drawn.

Track assignment

Between global and detailed routing, track assignment commits each global route to specific tracks on each layer. The core constraint is that two wires on the same track collide if their spans overlap along it, so this is a packing problem: the non-overlapping wire segments are packed onto each track, and segments that would overlap are pushed to different tracks, using as few tracks as the layer allows. It hands detailed routing a nearly complete solution, leaving mainly the local connections and rule-fixing to finish.

Maze routing

To connect one point to another around obstacles, detailed routers use maze routing (Lee's algorithm). It floods a wavefront outward from the source across the routing grid, labelling each reached cell with its distance from the source, until the wave reaches the target; then it backtraces from the target down the decreasing distances, which is guaranteed to trace a shortest legal path. Maze routing always finds a route if one exists, at the cost of searching many cells, so production routers steer the wave toward the target and confine it to a small window rather than flooding the whole grid.

Detailed routing and design rules

Detailed routing draws the exact wire and via geometry on legal tracks, obeying the full design-rule set: spacing, width, via rules, minimum area, and end-of-line rules, among many others. This is the hardest part of routing at advanced nodes, where the rules are numerous and interacting.

Because adjacent layers run in perpendicular preferred directions, every turn from a horizontal run to a vertical one costs a via, and each via adds resistance and delay and is a small yield risk. So the router also minimizes vias, taking fewer layer changes on a route where it can. This sits in tension with the reliability practice of doubling vias: a route uses as few vias as it can, then doubles the ones it must keep.

Pin access is often the limiting difficulty. Each pin exposes only a few legal points where a wire may land on it, its access tracks, and the pins of neighbouring cells compete for the same nearby tracks, so the router has to choose access points that do not block one another.

Congestion, rip-up, and reroute

Routing rarely succeeds in one pass. Where wires collide or a region has too little capacity, the router rips up offending nets and reroutes them along costlier but legal paths, repeating until no violations remain. Congestion that cannot be resolved sends the design back to placement or the floorplan, which is why congestion is watched from placement onward.

Timing-, crosstalk-, and manufacturing-aware routing

A wire is a circuit, so routing is not only about connectivity. Timing-driven routing keeps critical nets short and on fast layers. Crosstalk-aware routing spaces or shields aggressive nets so coupling does not corrupt timing or signals. Manufacturing-aware routing follows the extra rules of multi-patterning and inserts redundant vias and wire spreading to raise yield. Some nets must also be length-matched: the bits of a wide bus, or the two wires of a differential pair, are routed to nearly equal length, adding deliberate detours (serpentines) to the short ones, so they arrive together and their skew stays within budget. This matters most for synchronous buses and high-speed interfaces. Each of these adds a cost term to the same routing search.

Antenna and via reliability

During manufacturing, a long metal wire connected only to a gate can collect charge that damages the gate oxide, the antenna effect. Routing fixes it by breaking the wire with a jump to another layer or by adding a diode. Vias, the connections between layers, are a reliability and yield concern too, so routers prefer redundant double vias where space allows.

Where routing sits in the flow

Routing is the last construction stage before sign-off. It produces the final geometry that extraction turns into parasitics, which feed the sign-off timing, signal-integrity, and reliability checks. A design that will not route cleanly is not done, no matter how good its timing looked before, so routability is a constraint the whole flow is steered toward.