Buffer-level balancing (OCV)

Buffer-level balancing (on-chip variation). Balancing the nominal delay is not enough. Two clock paths that reach their flip-flops through a different number of buffer stages drift apart under on-chip variation, because process, voltage, and temperature shift each buffer a little and those shifts do not cancel unless the paths see the same stages. So a robust clock tree gives every sink the same buffer depth.

• Heavy branches buffered (slew) - the bold branches carry too much load to drive directly, so each one needs a buffer. That buffer also gives its sinks a stage.
• Every path same depth (OCV) - the light branches would otherwise reach their sinks with fewer stages. Add matching buffers on the shallow branches so every sink passes through the same number of stages. The on-chip-variation skew shown is the per-stage jitter times the stage mismatch; it must reach zero.

Placement matters: put each matching buffer where it lifts only the shallow sinks. Buffering an edge that also feeds a deep sink raises that sink too and unbalances it again. Match the depths, then Submit design.