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Planar, FinFET, Gate-All-Around

Foundry Processes foundational 1960s onward the industry the switch, three shapes

The idea

A MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is a switch: a gate electrode, separated from a semiconductor channel by a thin insulator, controls whether current flows between source and drain. Scaling the gate length makes the switch faster and smaller, but past a point the gate loses control of the channel: current leaks even when the switch is off. Each generation of transistor geometry is a way of giving the gate more control:

The measure that matters is how much of the channel's surface the gate touches relative to the channel volume it must control:

Planar: the gate touches the channel on one side only (the top); control degrades as gate length shrinks (short-channel effects).
FinFET: the channel is a thin vertical fin and the gate wraps three sides; strong control, and drive current comes in quanta of fins.
Gate-all-around (GAA), nanosheet: the channel is a stack of thin horizontal sheets and the gate surrounds each on all four sides; the best control, and drive strength tunes continuously with sheet width.

What each shape means for physical design

Planar (through 28/22 nm): device width is continuous, so cell designers size transistors freely; layout is the classic diffusion-and-poly picture.
FinFET (22/16 nm to 5/3 nm): width is quantized in fins, so drive strengths come in integer steps and cell heights are counted in fins (a 6-track cell might allow 2 fins per device). Fin pitch and the fixed gate pitch make cell layout a grid problem, and the library's drive-strength granularity coarsens.
Gate-all-around nanosheet (3/2 nm onward): sheet width is continuous again, so drive tunes finely, and stacking sheets gives more current per footprint. Successors under development stack an n-type device on top of a p-type one (CFET (Complementary Field-Effect Transistor)), halving cell footprint again.

The node name attached to each of these (7 nm, 5 nm, 3 nm) no longer corresponds to any drawn dimension; see the node-naming page.

Pros, cons, and the trade-off

Strengths of each step

FinFET restored off-state control and let scaling continue for a decade; it also raised drive per footprint.
Gate-all-around extends control further and gives back continuous width tuning.
Both reduce leakage per switch, the dominant power term at the end of the planar era.

Weaknesses

Fin quantization made cell design and drive-strength tuning coarser and constrained library architecture.
Process complexity and cost rise sharply at each transition; nanosheet stacks are among the hardest structures ever manufactured.
Parasitic capacitance of wrapped gates is high, so the delay win per node has shrunk while wire delay grew.

The trade-off

Every transistor generation trades manufacturing complexity for gate control. For the physical-design engineer the visible consequence is the library: continuous sizing gave way to fin counts and is coming back as sheet widths, and the cell template follows the device.

Where it stands today

Production: FinFET is the production device from 16/14 nm through 5/4 nm at every leading foundry; gate-all-around nanosheets entered production at 3 nm (Samsung, 2022) and 2 nm (TSMC and Intel announced for 2025).
Open PDKs (Process Design Kits): SKY130 and the other open kits are planar; ASAP7 (Arizona State University 7 nm predictive PDK (Process Design Kit)) is a FinFET model kit and is where the fin-count library structure can be studied openly.