Explore / Foundry Processes / On-Chip Variation and Derating

On-Chip Variation and Derating

Foundry Processes research 2000s onward sign-off methodology; tool vendors variation inside one die

The idea

A corner assumes every transistor on the die is at the same point of the distribution. They are not: random dopant fluctuation, line-edge roughness, and local layout effects make neighbouring devices differ. The danger is a timing check whose two sides see different variation: if the launching clock path is slow and the capturing clock path is fast, a hold check that passed at the corner can fail on silicon. OCV (On-Chip Variation) (On-Chip Variation) guards against it by derating the two sides in opposite directions:

setup check: launch path × (1 + d), capture path × (1 − d) ; hold check: launch × (1 − d), capture × (1 + d)
  • d the derate, a percentage from the foundry (a few to about ten percent per stage); early stages are sped up and late stages slowed down for setup, and the reverse for hold
  • launch path the clock path to the launching flop plus the data path
  • capture path the clock path to the capturing flop

Flat OCV (On-Chip Variation) is pessimistic: it derates every stage by the full amount, but variation partially averages out over a long path. Two refinements return that pessimism:

  • AOCV (Advanced On-Chip Variation) makes the derate a table of path depth (more stages, smaller derate) and physical distance (farther apart, larger derate).
  • POCV (Parametric On-Chip Variation) or SOCV (Statistical On-Chip Variation) gives each cell a delay sigma from the library and propagates variance along the path (root-sum-square), so the path's spread grows with the square root of depth, as it does physically. This is the practical form of statistical timing analysis that survived.

CPPR (Common Path Pessimism Removal) handles the other artefact: the part of the clock path shared by launch and capture cannot vary in opposite directions, so its derating is removed.

Pros, cons, and the trade-off

Strengths

  • Catches real failures: within-die mismatch on short paths is a genuine hold-failure mechanism.
  • Refinable: AOCV (Advanced On-Chip Variation) and POCV (Parametric On-Chip Variation) recover much of flat OCV (On-Chip Variation)'s pessimism without losing safety.

Weaknesses

  • Flat OCV (On-Chip Variation) is crude: uniform derates over-margin long paths and drive unnecessary fixes.
  • Library dependence: POCV (Parametric On-Chip Variation) needs per-cell sigma characterization the library must ship.
  • Complexity: derate tables, CPPR (Common Path Pessimism Removal), and multi-corner interaction make sign-off setups intricate and error-prone.

The trade-off

On-chip variation methodology is a ladder of pessimism reduction: flat derates are safe and wasteful, statistical propagation is tighter and more demanding. Each rung buys margin back at the cost of characterization and setup complexity, and advanced nodes climb it because the margin is worth more than the effort.

Where to see it

  • Open source: OpenSTA (the timing engine inside OpenROAD) supports timing derates and CPPR (Common Path Pessimism Removal); its statistical modes are limited compared with commercial tools.
  • Commercial: exposed as tool options. AOCV (Advanced On-Chip Variation) and POCV (Parametric On-Chip Variation) are standard sign-off options, and foundries supply the derate tables and sigma libraries per node.

References and further reading