Track Assignment
The idea
Global routing does not produce wires. It produces, for every net, a corridor: the chain of coarse GCells the net's wire is allowed to pass through, chosen for congestion and length at a resolution where the whole die is visible. Each GCell spans many real tracks, so a corridor fixes which columns and rows the wire will occupy but not which track it sits on. The figure builds the idea up from one net:
Detailed routing must turn those corridors into exact geometry. Running the full point-to-point search for every millimeter of every net wastes its power: most of a long net is one straight run whose position barely matters within its corridor. Track assignment is the intermediate pass that bulk-places those long runs. Each net's straight piece inside a region (an iroute) is an interval with a fixed extent; tracks are rows; two iroutes conflict when their extents overlap:
panela horizontal (or vertical) strip of the die, one track-pitch tall stack of parallel tracks[l, r]the iroute's extent along the panel, fixed by its global route guide
This is the left-edge problem again, six decades on: sort by left endpoint, first-fit into tracks. Production formulations add weights for via count, pin alignment, and overlap with blockages, and solve the same packing greedily or as a small assignment problem per panel.
The recipe
Step 1 (extract and sort). Cut the die into panels aligned with the routing layers' preferred directions. Within each panel, extract each net's iroute from its route guide: the long straight run between the net's pin columns, whose extent [l, r] the guide fixes and whose track is still free. Sort the iroutes by left endpoint (by length or criticality in weighted forms).
Step 2 (place). Sweep the sorted list and place each iroute on the first track where it fits without overlap, exactly the left-edge sweep. Its endpoints are recorded as future vias where the pin connections will land.
Step 3 (hand off). Fix the assigned trunks. The detail router now only connects pins to trunks, short perpendicular stubs landing on those vias, and repairs local rule violations: short searches instead of long ones.
Watch it work: packing iroutes
One panel, four tracks, five nets crossing it. The walkthrough follows the stage from what global routing handed over (pins and route guides) through iroute extraction, the sort, one placement per step with the fit test's arithmetic, the check against the guides, and the pin-to-trunk hand-off to detailed routing.
Pros, cons, and the trade-off
Strengths
- Search where it pays: the expensive A* (A-star) search is spent on short pin connections, not on kilometers of straight trunk.
- Proven core: the interval-packing engine is the left-edge greedy, simple, near-linear, and well understood.
- Panel parallelism: panels are independent and are assigned concurrently.
- Better starting point: detail routing that starts from assigned trunks converges in fewer rip-up iterations.
Weaknesses
- Commitments made blind: trunks are placed before full design rules are checked; some assignments must be torn up later anyway.
- Panel boundaries: nets crossing panels need consistent assignments on both sides, which the per-panel view complicates.
- Weighted reality: the clean optimality of pure interval packing disappears once via and alignment costs enter; production versions are heuristic.
The trade-off
Track assignment inserts one more resolution between the corridor and the coordinate, buying detail routing a massive head start at the cost of commitments made without full rule knowledge. It is also the field's cleanest example of an algorithm outliving its era: the channel router died, and its greedy heart was reborn inside the flow that replaced it.
Is it actually used today?
The evidence for track assignment comes from open-source detailed routers, vendor publications, and the algorithm's lineage.
- Open source: TritonRoute, OpenROAD's detailed router, runs an explicit track-assignment stage between reading the route guides and the DRC (Design Rule Check) driven search iterations.
- Commercial: better evidenced than most internals. The 2002 Batterywala et al. paper proposing the stage came out of Synopsys, and vendor documentation and patents describe track assignment as a step between global and detailed routing. The exact packing heuristics inside Innovus, Fusion Compiler, and Aprisa are proprietary; that the stage exists is documented, how it is solved is inference.
- The lineage: the packing core is the left-edge algorithm of 1971, covered on its own page in the historical family.