The BEOL (Back End Of Line) Stack and Damascene Copper
The idea
The FEOL (Front End Of Line) builds the transistors; the BEOL (Back End Of Line) builds everything above them: the metal layers, the vias, and the dielectric between. Since 1997 the metal has been copper, and copper cannot be etched cleanly, so each layer is made by damascene: carve the pattern into the dielectric, fill it with metal, polish away the excess:
One BEOL (Back End Of Line) layer is built in six steps:
Step 1 (deposit). A slab of dielectric goes over the finished layer below.
Step 2 (pattern and etch). Lithography defines the via holes down to the layer below and the wire trenches, and both are etched into the slab before any metal exists (dual damascene). The multi-patterning constraints of the routing section act here, and the plasma etch is where the antenna effect deposits its charge.
Step 3 (barrier and seed). A thin tantalum-based liner coats every surface so copper cannot diffuse into the dielectric, plus a copper seed for plating. The liner conducts poorly and does not thin with the pitch; at fine widths it consumes a large fraction of the wire's cross-section.
Step 4 (fill). Copper is electroplated, filling via and trench in one step and overfilling the surface.
Step 5 (polish). CMP (Chemical-Mechanical Polishing) planarizes the surface. It thins wide metal and dishes sparse regions, which is why density rules and dummy fill exist.
Step 6 (cap). A dielectric cap seals the copper before the next layer's slab is deposited.
The process repeats for every layer, thin layers first at fine pitch, thick layers last at coarse pitch, and each layer's etch is a plasma step: the antenna effect (routing section) is the charge those etches deposit on wires that already connect to gates.
What the process order explains
- Vias are separate objects with their own rules because they are separate holes etched before the trench above them.
- Wide wires are thinner than drawn after CMP (Chemical-Mechanical Polishing), so their resistance is worse than area suggests (dishing); spacing tables and slotting rules follow.
- Density fill is required so CMP (Chemical-Mechanical Polishing) sees a uniform surface; the flow inserts floating dummy metal after routing, and it adds capacitance the extractor must see.
- Barrier thickness does not scale with pitch, so at advanced nodes the conducting copper core of a minimum wire is a shrinking fraction of its cross-section, and resistance per length rises faster than geometry alone predicts.
Pros, cons, and the trade-off
Strengths
- Copper: about 40 percent lower resistivity than the aluminium it replaced, and better electromigration life.
- Dual damascene: via and wire in one metallization step, fewer process steps per layer.
- Planar every layer: CMP (Chemical-Mechanical Polishing) makes stacks of 15 layers manufacturable.
Weaknesses
- Barrier overhead at fine pitch, driving the search for barrier-less metals (cobalt, ruthenium) on the lowest layers.
- Dielectric constant: the low-k materials that cut capacitance are mechanically weak.
- Design-rule consequences: fill, density, dishing, and via rules exist to keep this process in its window, and the design pays for each.
The trade-off
Damascene copper made the many-layer stack possible and defined the interconnect era; its process window is why the metal rules look the way they do. At the finest pitches its own liner is now the limit, and the industry is changing metals on the bottom layers to escape it.
Where it stands today
- Copper dual damascene is the BEOL (Back End Of Line) of every process from 180 nm to the current leading edge.
- Cobalt and ruthenium replace copper on the lowest, finest layers at some foundries from the 10/7 nm generations onward, because their thin or absent liners beat copper's at that width.
- The rules a physical-design engineer meets (fill, density, via enclosure, antenna) all trace to steps in this sequence.