Static Timing Propagation

The idea

Simulating enough vectors to exercise a billion paths is impossible; static timing sidesteps input patterns entirely. Model the design as a directed acyclic graph: nodes are pins, edges are gate arcs (input pin to output pin, with delay from characterized libraries) and net arcs (driver to sinks, with interconnect delay). Process nodes in topological order, propagating arrival time: each node's arrival is the maximum over incoming edges of source arrival plus edge delay (maximum for setup analysis; a parallel minimum propagation serves hold). Then sweep backward propagating required time from the constraints at endpoints (capture clock edge minus setup, as this site's slack quiz drills). Then, at every node:

• slack timing margin at the node: positive means met, negative means violated
• required latest allowed arrival, propagated backward from the constraints
• arrival actual worst-case arrival, propagated forward from the clocks

Negative slack marks the violating cone, and the worst path is recovered by walking maximizing predecessors.

Two sweeps of the graph, linear in circuit size, cover every path implicitly. Rising and falling transitions propagate as separate values, slews propagate alongside arrivals (each arc's delay depends on input slew and output load), and multiple clocks, exceptions (false paths, multicycles), and min/max corners multiply the bookkeeping without changing the algorithm.

The fine print

Exhaustiveness buys conservatism: the timer happily reports paths that no logic value could ever sensitize (false paths), which is why exception commands exist and why the SDC (Synopsys Design Constraints) file, as this site's constraints problem insists, is half the analysis.

Where you meet it today

report_checks in OpenSTA, inside every synthesis, placement, and routing optimization loop as the incremental oracle, and at sign-off, where this computation is the final word on shipping.