Hierarchical Macro Placement (Hier-RTLMP)

The idea

Real chips arrive with hundreds of memory macros and a logical hierarchy that already encodes designer intent. Hier-RTLMP, the macro placer in OpenROAD, leans into both. It builds a physical hierarchy by clustering the netlist, guided by the RTL (Register Transfer Level) module tree and by dataflow analysis (which clusters feed which through how many registers), producing a tree of clusters whose leaves are macro groups and standard-cell clusters.

Placement then proceeds top-down through the tree. Each cluster's children are shaped (tileable aspect-ratio ranges computed from their contents) and placed inside the parent's outline by simulated annealing on a packing representation, with a cost that mixes wirelength, outline fit, congestion proxies, and guidance terms: dataflow affinities pull talkative clusters together, boundary and corner biases push macro arrays to die edges so the core stays open for standard cells, and blockage awareness respects what floorplanners actually fear. Leaf level places the individual macros; standard-cell regions are left for the global placer.

Why the hierarchy matters

Flat annealing over hundreds of macros plus abstract cell area is slow and aimless; the hierarchy cuts the problem into annealing runs of manageable size and injects structural knowledge annealing cannot discover: this cache belongs with that datapath because the RTL (Register Transfer Level) tree and the dataflow say so. It is the same divide-and-guide instinct as min-cut floorplanning, rebuilt with modern clustering and cost design.

Where you meet it today

Type rtl_macro_placer in OpenROAD: this is the production macro placement of the open-source flow, and its papers document strong results against both human floorplans and flat automatic ones on industrial testcases.