Games / Command flash cards / Layout and parasitic formats

Layout and parasitic formats read against real files

Choose a section to drill, or play every section mixed together. Each section lists the commands it covers, and any kinds of card it holds besides the plain one: a command whose meaning you pick.

SourceFour formats carry a design between tools: LEF (Library Exchange Format) for the technology and the cells, DEF (Design Exchange Format) for the layout, SPEF (Standard Parasitic Exchange Format) for extracted wires, and SDF (Standard Delay Format) for annotated delays. The LEF (Library Exchange Format) excerpts here are quoted from the Nangate45 files that OpenROAD-flow-scripts ships; the rest follow the formats as OpenROAD and OpenSTA read them. Reference: the OpenSTA command reference (the open flow on GitHub).

All sections

A mixed round drawn from every section. Due cards come first, then new cards in random order.

53cards across 8 sections
mixed round play

LEF (Library Exchange Format) technology

Layers, their electrical properties, and the rules the router obeys.

LAYERTYPEWIDTHSPACINGPITCHDIRECTIONRESISTANCESPACINGTABLEVIASITE
9 cards play

LEF (Library Exchange Format) macros

What a cell or a hard macro looks like from the outside.

MACROCLASSSIZESYMMETRYORIGINPINPORTOBSANTENNAGATEAREA
8 cards play

DEF (Design Exchange Format)

The design's own layout: area, rows, instances, pins, and wires.

UNITSDIEAREAROWTRACKSCOMPONENTSPINSNETSSPECIALNETSVIASREGIONS
10 cards play

SPEF (Standard Parasitic Exchange Format)

Extracted parasitics: the resistance and capacitance of every net.

D_NETCONNCAPREScouplingname-maptriplets
6 cards play

SDF (Standard Delay Format)

Delays and checks handed from one tool to another.

CELLIOPATHSETUPHOLDINTERCONNECTCONDtriplets
6 cards play

GDSII (Graphic Design System II) and mask data

The binary layout the foundry is sent, and how it relates to everything above it.

structureboundarylayerdatatypelayer mapOASISXOR
5 cards play

Netlists

The connectivity itself, at gate level for the tools and transistor level for the checks.

moduleinstanceescaped namesbus bitsCDLsubcircuit
3 cards play

How they fit together

Which file answers which question, and what happens when one disagrees.

read_lefread_defread_spefread_sdfwrite_defwrite_spef
6 cards play