Anatomy of a PDK (Process Design Kit)
The idea
A PDK (Process Design Kit) is everything a design team needs to produce a manufacturable layout for one process without knowing how the process is built. Its contents map onto the flow's stages almost one to one:
A kit has four parts:
- Technology description: the layer stack, routing pitches and directions, via definitions, and the design rules the tools enforce during layout; delivered as a technology LEF (Library Exchange Format) file for place-and-route plus rule files for the sign-off tools.
- Cell library: the standard cells (and often memories and I/O (Input/Output) cells) as abstract geometry for placement and routing (cell LEF (Library Exchange Format)), timing and power models (Liberty), and full layout for the final tape-out (GDSII (Graphic Design System II) or OASIS (Open Artwork System Interchange Standard)).
- Verification decks: the DRC (Design Rule Check), LVS (Layout Versus Schematic), and antenna rule decks the sign-off tools run against the finished layout.
- Models: transistor SPICE (Simulation Program with Integrated Circuit Emphasis) models for circuit simulation, and parasitic-extraction tables (resistance and capacitance per layer and geometry) so the timing tools can estimate wire delay.
The place-and-route flow reads only the abstractions: it never sees a transistor. It sees cells as boxes with pins and blockages, layers as track grids with capacities and rules, and timing as lookup tables. The full geometry is merged in only at the end, when the routed abstract layout is combined with the cell layouts into the tape-out database.
The files, with SKY130 examples
Every kind of file below is a real, public file from the SKY130 kit
as packaged in the OpenROAD flow's sky130hd platform (the platform
this site's graded problems run on). Open one to see what the flow
actually reads.
| file kind | what it holds | who reads it | SKY130 example |
|---|---|---|---|
| technology LEF (Library Exchange Format) | layers, pitches, directions, via definitions, spacing tables, antenna parameters | floorplan, place, CTS (Clock Tree Synthesis), route | sky130_fd_sc_hd.tlef |
| cell LEF (Library Exchange Format) | per cell: size, site, pin shapes and layers, obstructions | floorplan, place, CTS (Clock Tree Synthesis), route | sky130_fd_sc_hd_merged.lef |
| Liberty (.lib) | per cell and arc: delay and slew tables, power, leakage, at one PVT (Process, Voltage, Temperature) corner | synthesis, place, CTS (Clock Tree Synthesis), STA (Static Timing Analysis) | sky130_fd_sc_hd__tt_025C_1v80.lib (typical corner; the full library ships every corner) |
| parasitic tables | wire resistance and capacitance per layer and pattern for extraction | STA (Static Timing Analysis) after routing | rcx_patterns.rules; the pre-route estimates in setRC.tcl |
| DRC (Design Rule Check) deck | every geometric rule the layout must satisfy | sign-off | sky130hd.lydrc (KLayout deck); the rules themselves in the SKY130 periphery rules |
| LVS (Layout Versus Schematic) deck | device and connectivity extraction to compare layout against netlist | sign-off | sky130hd.lylvs |
| cell layouts, GDSII (Graphic Design System II) | full mask geometry of every cell, merged with the routing at tape-out | sign-off, tape-out | sky130_fd_sc_hd.gds |
| SPICE (Simulation Program with Integrated Circuit Emphasis) models | transistor and device models for circuit simulation and characterization | library characterization, analog design | sky130_fd_pr primitives |
| flow configuration | which of the above the flow uses, plus site, rows, power-grid recipe | the flow itself | config.mk, pdn.tcl (power grid) |
The upstream kit lives at the SkyWater PDK (Process Design Kit) repository; the open_pdks project packages it into the directory layout most open tools expect.
Where each file is consumed
Technology LEF (Library Exchange Format) is read at floorplanning and drives every later stage: routing layer names, preferred directions, pitches, minimum widths and spacings, via rules, and antenna parameters. The router's track grid is built from it.
Cell LEF (Library Exchange Format) is read with the technology LEF (Library Exchange Format): each cell's size, pin shapes and layers, and internal obstructions. Placement legalizes to the site width and row height it defines; the router accesses the pins it draws.
Liberty (.lib) is read by synthesis and by STA (Static Timing Analysis): per cell, per arc, delay and output slew as tables of input slew and output load, plus leakage and switching power, at one PVT (Process, Voltage, Temperature) (Process, Voltage, Temperature) corner per file.
Parasitic tables (in OpenROAD, the RCX (Resistance-Capacitance eXtraction) rules file) are read after routing to turn wire geometry into resistances and capacitances for the timing tools.
DRC (Design Rule Check) and LVS (Layout Versus Schematic) decks are read by the sign-off tools on the merged layout: DRC (Design Rule Check) proves every shape obeys the rules, LVS (Layout Versus Schematic) proves the drawn transistors and wires match the netlist.
Pros, cons, and the trade-off
Strengths of the abstraction
- Portability: the same flow runs on any process that ships the same file kinds; changing PDK (Process Design Kit) is changing inputs, not tools.
- Scale: boxes-with-pins and lookup tables let a router handle billions of shapes that no transistor-level tool could.
- Protection: the foundry discloses rules and models, not how the process is built.
Weaknesses
- Abstraction gaps: LEF (Library Exchange Format) capacities approximate real rules; a route legal in the abstraction can fail sign-off DRC (Design Rule Check).
- Corner explosion: one Liberty file per corner, and modern nodes need dozens.
- Kit quality varies: a poorly characterized library or an incomplete deck costs the design team weeks, and they cannot fix it themselves.
The trade-off
The PDK (Process Design Kit) trades fidelity for tractability at every interface: the flow works on abstractions precisely so that it can work at all, and every abstraction is a place where the sign-off tools may later disagree. Knowing which file feeds which stage is knowing where those disagreements can come from.
Where to see one
- Open source: the SkyWater SKY130 PDK (Process Design Kit) publishes every file kind above and is the process this platform's graded problems run on; its documentation is the most complete public tour of a PDK (Process Design Kit).
- The flow's view: OpenROAD's platform directories show exactly which PDK (Process Design Kit) files a place-and-route flow consumes and which it ignores.
- Commercial kits: structurally the same, delivered under NDA (Non-Disclosure Agreement), with far larger libraries and many more corners.