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Wire Resistance, Capacitance, and Why Interconnect Dominates

Foundry Processes research the scaling arithmetic the delay moved into the wires

The idea

A wire is a distributed resistance and capacitance. Its delay to first order is the Elmore delay, and for a uniform wire that scales with the square of its length:

delay ≈ 0.38 × r × c × L² (unbuffered wire) ; r = ρ / (w × t) ; c ≈ ε × (t / s + w / h)

r resistance per unit length: resistivity ρ over cross-section (width w times thickness t); halving width and thickness together quadruples r
c capacitance per unit length: sidewall coupling to neighbours at spacing s plus plate capacitance to the layers above and below at distance h; it barely falls with scaling because everything shrinks together
L wire length; the quadratic term is why long wires are broken with buffers into segments whose delay adds linearly
ρ effective resistivity, which itself rises at fine widths (electron scattering at surfaces and grain boundaries, plus the non-scaling barrier)

Scaling shrinks a gate and makes it faster; scaling shrinks a wire's cross-section and makes it slower per unit length, while the chip's long wires stay long. Around the 130 nm generation the delay of a global wire overtook a gate delay, and at advanced nodes even local wires matter: timing is decided by routing, which is why the flow iterates routing and STA (Static Timing Analysis) together.

The consequences the flow lives with

Buffering: a long wire is split into segments with repeaters so delay grows linearly with length instead of quadratically; repeater insertion is a placement-and-routing-time optimization.
Layer promotion: critical long nets move to thick upper metal where r is several times lower (the layer-assignment page in routing).
Timing depends on routing: pre-route timing estimates carry wireload models or Steiner estimates; post-route parasitics from extraction are the truth, and the two can differ enough to reopen closure.
Coupling capacitance between neighbours is a large fraction of c at fine pitch, which is why crosstalk-aware routing exists.

Pros, cons, and the trade-off

What still improves

Local wires shrink with the cells they connect, so their absolute delay stays tolerable.
Thick upper layers keep global delay in check when critical nets are promoted.
Buffering converts the L² problem into a linear one at the cost of area and power.

What gets worse

Resistance per length of minimum wires rises faster than geometry predicts, because of resistivity and barrier effects.
Via resistance becomes a significant fraction of path delay at fine pitch.
Power: charging wire capacitance is a large share of dynamic power, and repeaters add more.

The trade-off

Scaling helped transistors and hurt wires, and the flow's architecture is the response: routing-aware placement, timing-driven routing, repeaters, and layer promotion all exist because delay moved into the interconnect. A physical-design engineer's job is largely managing that migration.

Where to see the numbers

Per-layer r and c values are in every PDK (Process Design Kit)'s parasitic tables; for SKY130 they are public, and OpenROAD's RCX (Resistance-Capacitance eXtraction) rules file lists them.
The IRDS (International Roadmap for Devices and Systems) interconnect chapters chart resistivity and delay trends across generations.