Games / Command flash cards / Layout and parasitic formats / Netlists

Netlists

Each card shows a command to explain. A missed card returns later in the round and starts the schedule over. A card answered correctly moves up the schedule and next appears after 1, 3, 7, then 21 days. Keys 1 to 4 choose an option, h shows a hint, and Enter moves on. A hint keeps the card where it is on the schedule. An ordering card is answered by clicking its items in order, and one wrong click ends it. Time values are in nanoseconds. Progress is stored in this browser.

SourceFour formats carry a design between tools: LEF (Library Exchange Format) for the technology and the cells, DEF (Design Exchange Format) for the layout, SPEF (Standard Parasitic Exchange Format) for extracted wires, and SDF (Standard Delay Format) for annotated delays. The LEF (Library Exchange Format) excerpts here are quoted from the Nangate45 files that OpenROAD-flow-scripts ships; the rest follow the formats as OpenROAD and OpenSTA read them. Reference: the OpenSTA command reference (the open flow on GitHub).
All 3 cards in this section, with answers
  • module gcd (clk, req_msg, resp_msg); input clk; INV_X1 _897_ (.A(_039_), .ZN(_040_)); DFF_X1 _898_ (.D(_040_), .CK(clk), .Q(resp_msg[3])); endmodule
    A gate-level netlist: library cells wired together, and nothing else.

    Hint: There is no always block and no operator anywhere in it.

    Synthesis turns behaviour into this. Every instance is a cell from the Liberty and LEF (Library Exchange Format) libraries, so the same file can be timed, placed, and routed. It is also what formal equivalence compares against the register-transfer source. the open flow reference

  • \dpath.a_reg[9]$_DFFE_PP_ ( .D(...) );
    An escaped name, so characters that normally mean something are literal.

    Hint: Note the leading backslash and where the name ends.

    A backslash starts an escaped identifier and a space ends it, which is how a name can contain brackets, dots, or a dollar sign. Scripts that build a name by hand and forget the trailing space are a familiar source of a constraint that silently matches nothing. the open flow reference

  • .SUBCKT INV_X1 A ZN VDD VSS M0 ZN A VDD VDD PMOS_VTL W=0.415u L=0.05u M1 ZN A VSS VSS NMOS_VTL W=0.415u L=0.05u .ENDS
    A transistor-level netlist, which the layout is checked against.

    Hint: The instances are not cells. Ask what they are, and which check needs them.

    Layout versus schematic extracts devices from the polygons and compares them with this file, so a cell library ships one. It is the reason a design hands off both a gate-level netlist and, for the cells and any analog blocks, a transistor-level one. the open flow reference