Games / Command flash cards / Layout and parasitic formats / LEF (Library Exchange Format) technology

LEF (Library Exchange Format) technology

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SourceFour formats carry a design between tools: LEF (Library Exchange Format) for the technology and the cells, DEF (Design Exchange Format) for the layout, SPEF (Standard Parasitic Exchange Format) for extracted wires, and SDF (Standard Delay Format) for annotated delays. The LEF (Library Exchange Format) excerpts here are quoted from the Nangate45 files that OpenROAD-flow-scripts ships; the rest follow the formats as OpenROAD and OpenSTA read them. Reference: the OpenSTA command reference (the open flow on GitHub).
All 9 cards in this section, with answers
  • LAYER metal1 TYPE ROUTING ; SPACING 0.065 ; WIDTH 0.07 ; PITCH 0.14 ; DIRECTION HORIZONTAL ;
    The minimum width and spacing, and the pitch that follows.

    Hint: Compare WIDTH, SPACING, and PITCH: two of them add up to the third.

    Width and spacing are minimums for the layer, and the pitch follows from them: 0.14 is the minimum width of 0.07 plus the minimum spacing of 0.065, rounded to the manufacturing grid. DIRECTION gives the preferred routing direction, which alternates up the stack so crossing wires can meet at vias. the open flow reference

  • RESISTANCE RPERSQ 0.38 ; CAPACITANCE CPERSQDIST 7.7161e-05 ; EDGECAPACITANCE 2.7365e-05 ; THICKNESS 0.13 ;
    The layer's electrical properties, used to estimate wire delay.

    Hint: Ask which tool reads these, given that they are not geometric rules.

    Resistance per square and capacitance per unit area are what turn a wire's geometry into an RC (Resistance-Capacitance) delay, which is what set_layer_rc overrides and estimate_parasitics uses. Edge capacitance accounts for the sidewalls, which dominate at small geometries. the open flow reference

  • SPACINGTABLE PARALLELRUNLENGTH 0.0000 2.7000 4.0000 WIDTH 0.0000 0.8000 0.8000 0.8000 WIDTH 0.9000 0.8000 0.9000 0.9000 WIDTH 1.5000 0.8000 0.9000 1.5000 ;
    Required spacing keyed by wire width and how far two wires run alongside.

    Hint: Two axes. Ask what makes the required spacing grow along each.

    Two wide wires running beside each other for a long distance need more space than a short narrow pair, both for manufacturing and for coupling. This is the table form of the wide-metal spacing rule, and it is why a non-default rule that widens a net must widen its spacing too. the open flow reference

  • SITE FreePDK45_38x28_10R_NP_162NW_34O CLASS CORE ; SIZE 0.19 BY 1.4 ; END
    The placement unit that rows and cell widths are built from.

    Hint: Ask what a row is built from, and what every cell's width is a multiple of.

    Rows are one site tall and cell widths are whole multiples of one, which is what makes legalization possible: every legal position is a site, and every legal cell width is a multiple of one. initialize_floorplan -site names it, and a library belongs to a site as much as to a process. the open flow reference

  • UNITS DATABASE MICRONS 2000 ; END UNITS MANUFACTURINGGRID 0.0050 ;
    The database resolution, and the coarser grid every shape must land on.

    Hint: Two different grids. One is how finely a number can be written, the other what may be made.

    A resolution of 2000 means one database unit is half a nanometre, so coordinates are integers. The manufacturing grid is 5 nanometres, and a shape off that grid cannot be made, which is why legalization snaps everything to it. The two numbers are independent. the open flow reference

  • BUSBITCHARS "[]" ; DIVIDERCHAR "/" ;
    The characters that mark a bus bit and a hierarchy level in names.

    Hint: Think about how an instance deep in the hierarchy is named in a report.

    A pin is out[3] and an instance inside a block is core/reg_1. Tools that disagree about these characters produce names that do not match across files, which is a common cause of a constraint matching nothing. An instance whose real name contains a bracket has to escape it. the open flow reference

  • LAYER poly TYPE MASTERSLICE ; END poly
    A layer that exists in the process but that the router may not use.

    Hint: Compare with a layer declared as ROUTING or CUT.

    Polysilicon and diffusion appear so that contacts and antenna rules can refer to them, but only ROUTING layers carry routes and only CUT layers carry vias. Declaring a layer with the wrong type is a quick way to make a router either ignore metal or try to route on diffusion. the open flow reference

  • VIA via1_4 DEFAULT LAYER via1 ; RECT -0.035 -0.035 0.035 0.035 ; END via1_4 VIARULE Via1Array-0 GENERATE LAYER metal1 ; ENCLOSURE 0.035 0.035 ; LAYER via1 ; SPACING 0.15 BY 0.15 ; END Via1Array-0
    A fixed via, and a rule for building a via array of any size.

    Hint: One is a finished object, the other a recipe.

    The named vias are what a router drops between two routing layers. The generate rule says how to build a larger array, giving the metal enclosure on each side and the spacing between cuts, which is what the power grid uses where it needs many cuts to carry current. the open flow reference

  • LAYER via1 TYPE CUT ; SPACING 0.08 ; RESISTANCE 5 ; END via1
    The resistance of one via cut, counted once per cut.

    Hint: The number is in ohms, and it is not per unit length.

    Five ohms a cut is large next to a short wire, which is why extraction counts vias and why a route that changes layer repeatedly is slower than its length suggests. Doubling the cuts halves the resistance, which is what a via array is for. the open flow reference