Games / Command flash cards / Layout and parasitic formats / SDF (Standard Delay Format)

SDF (Standard Delay Format)

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SourceFour formats carry a design between tools: LEF (Library Exchange Format) for the technology and the cells, DEF (Design Exchange Format) for the layout, SPEF (Standard Parasitic Exchange Format) for extracted wires, and SDF (Standard Delay Format) for annotated delays. The LEF (Library Exchange Format) excerpts here are quoted from the Nangate45 files that OpenROAD-flow-scripts ships; the rest follow the formats as OpenROAD and OpenSTA read them. Reference: the OpenSTA command reference (the open flow on GitHub).
All 6 cards in this section, with answers
  • (CELL (CELLTYPE "INV_X1") (INSTANCE _897_) (DELAY (ABSOLUTE (IOPATH A ZN (0.012:0.014:0.019) (0.011:0.013:0.017)))))
    The rising and falling delay from A to ZN, as three values.

    Hint: Two bracketed groups of three numbers. Ask what each group and each number is.

    The three numbers are minimum, typical, and maximum. SDF (Standard Delay Format) carries computed delays per instance, so another tool can time or simulate without repeating delay calculation. The triplet is the standard min, typical, max form, and the two groups are the output's two directions. the open flow reference

  • (TIMINGCHECK (SETUP D (posedge CK) (0.031)) (HOLD D (posedge CK) (0.012)))
    The setup and hold requirements of that instance, annotated from the file.

    Hint: Ask what these two lines are, given that they are not delays.

    Checks are annotated separately from delays, which is why OpenSTA reports their coverage separately with report_annotated_check. The values replace the library's, so a design timed with an SDF (Standard Delay Format) file may not match one timed from Liberty alone. the open flow reference

  • (INTERCONNECT _897_/ZN _124_/D (0.004:0.005:0.007))
    The wire delay from one instance pin to another.

    Hint: Ask which part of a path this covers, given that IOPATH covers the cells.

    Cell delays come as IOPATH entries and wire delays as INTERCONNECT entries, one per driver-to-load pair. Annotating both is how a simulation reproduces exactly the timing the analysis saw. the open flow reference

  • (COND A2 == 1'b0 (IOPATH A1 ZN (0.018:0.021:0.026) (0.016:0.019:0.024)))
    A delay that applies only while that condition holds.

    Hint: Compare it with the same idea in a Liberty file.

    It matches the library's conditional arc for the same pins. A gate's delay depends on its other inputs, so conditional arcs exist in the library and must survive into the annotation. This is what sdf_cond in Liberty is for: it gives the condition in the syntax an SDF (Standard Delay Format) writer needs so the two line up. the open flow reference

  • (SDFVERSION "3.0") (DESIGN "gcd") (VOLTAGE 1.100::1.100) (PROCESS "1.000::1.000") (TEMPERATURE 25.000::25.000) (TIMESCALE 1ns)
    The corner the delays hold for, and the unit they are written in.

    Hint: Ask what would have to change for a second file to be needed.

    One file is one corner. A simulation at another voltage or temperature needs its own, which is why a regression annotates a different file for each corner it runs. The timescale sets what a bare number means, so reading a file that assumes nanoseconds as picoseconds is silently wrong. the open flow reference

  • (IOPATH A1 ZN (0.023::0.023) (0.022::0.022)) (SETUP (posedge D) (posedge CK) (0.030::0.032))
    Minimum and maximum for each value, with rise and fall given separately.

    Hint: Count the numbers in each bracket, and count the brackets.

    The format allows three values separated by colons, but a missing middle one leaves the pair written here. The first bracket of an arc is the rising output and the second the falling. For a check, the two values are the fast and slow versions of the same requirement. the open flow reference