Games / Command flash cards / Layout and parasitic formats / All sections

All sections

Each card shows a command to explain. A missed card returns later in the round and starts the schedule over. A card answered correctly moves up the schedule and next appears after 1, 3, 7, then 21 days. Keys 1 to 4 choose an option, h shows a hint, and Enter moves on. A hint keeps the card where it is on the schedule. An ordering card is answered by clicking its items in order, and one wrong click ends it. Time values are in nanoseconds. Progress is stored in this browser.

SourceFour formats carry a design between tools: LEF (Library Exchange Format) for the technology and the cells, DEF (Design Exchange Format) for the layout, SPEF (Standard Parasitic Exchange Format) for extracted wires, and SDF (Standard Delay Format) for annotated delays. The LEF (Library Exchange Format) excerpts here are quoted from the Nangate45 files that OpenROAD-flow-scripts ships; the rest follow the formats as OpenROAD and OpenSTA read them. Reference: the OpenSTA command reference (the open flow on GitHub).

All 53 cards in this deck, with answers

LAYER metal1 TYPE ROUTING ; SPACING 0.065 ; WIDTH 0.07 ; PITCH 0.14 ; DIRECTION HORIZONTAL ;

The minimum width and spacing, and the pitch that follows.

Hint: Compare WIDTH, SPACING, and PITCH: two of them add up to the third.

Width and spacing are minimums for the layer, and the pitch follows from them: 0.14 is the minimum width of 0.07 plus the minimum spacing of 0.065, rounded to the manufacturing grid. DIRECTION gives the preferred routing direction, which alternates up the stack so crossing wires can meet at vias. the open flow reference
RESISTANCE RPERSQ 0.38 ; CAPACITANCE CPERSQDIST 7.7161e-05 ; EDGECAPACITANCE 2.7365e-05 ; THICKNESS 0.13 ;

The layer's electrical properties, used to estimate wire delay.

Hint: Ask which tool reads these, given that they are not geometric rules.

Resistance per square and capacitance per unit area are what turn a wire's geometry into an RC (Resistance-Capacitance) delay, which is what set_layer_rc overrides and estimate_parasitics uses. Edge capacitance accounts for the sidewalls, which dominate at small geometries. the open flow reference
SPACINGTABLE PARALLELRUNLENGTH 0.0000 2.7000 4.0000 WIDTH 0.0000 0.8000 0.8000 0.8000 WIDTH 0.9000 0.8000 0.9000 0.9000 WIDTH 1.5000 0.8000 0.9000 1.5000 ;

Required spacing keyed by wire width and how far two wires run alongside.

Hint: Two axes. Ask what makes the required spacing grow along each.

Two wide wires running beside each other for a long distance need more space than a short narrow pair, both for manufacturing and for coupling. This is the table form of the wide-metal spacing rule, and it is why a non-default rule that widens a net must widen its spacing too. the open flow reference
SITE FreePDK45_38x28_10R_NP_162NW_34O CLASS CORE ; SIZE 0.19 BY 1.4 ; END

The placement unit that rows and cell widths are built from.

Hint: Ask what a row is built from, and what every cell's width is a multiple of.

Rows are one site tall and cell widths are whole multiples of one, which is what makes legalization possible: every legal position is a site, and every legal cell width is a multiple of one. initialize_floorplan -site names it, and a library belongs to a site as much as to a process. the open flow reference
MACRO INV_X1 CLASS core ; ORIGIN 0 0 ; SYMMETRY X Y ; SITE FreePDK45_38x28_10R_NP_162NW_34O ; SIZE 0.38 BY 1.4 ;

The cell's outline and the flips it allows, on the site it belongs to.

Hint: One of these lines is what lets a placer flip the cell.

SYMMETRY X Y says the cell may be mirrored about either axis, which is what optimize_mirroring uses and what lets rows alternate orientation and share rails. CLASS core marks it a standard cell; a hard macro is CLASS BLOCK, and a pad is CLASS PAD. the open flow reference
PIN A DIRECTION INPUT ; PORT LAYER metal1 ; POLYGON 0.06 0.525 0.165 0.525 0.165 0.7 0.06 0.7 ; END END A

The pin's direction and the shapes the router must reach.

Hint: Ask what the router needs to know about a pin beyond its name.

The layer is named with the shapes. A pin can have several ports and several shapes, which is why a router computes access points rather than aiming at a coordinate. Everything the outside world may touch is here; the cell's insides are not in LEF (Library Exchange Format) at all. the open flow reference
OBS LAYER metal1 ; RECT 0.0 0.0 0.38 1.4 ; END

Blocked area: metal inside the cell that routing must avoid.

Hint: It is inside the macro but is not a pin. Ask what it forbids.

The cell's internal wiring already occupies parts of the lower layers, so the router must know where it cannot put its own. On a hard macro, obstructions over several layers are what force routing to go around or above it. the open flow reference
ANTENNAGATEAREA 0.05225 ; ANTENNAPARTIALMETALAREA 0.018375 LAYER metal1 ;

The gate and metal areas the antenna check compares.

Hint: Ask which check needs a ratio between two areas.

The ratio between them is what the rule limits: metal area against the gate area it connects to, so the library has to declare the gate area behind each pin and the metal the cell itself already contributes. check_antennas adds the routed metal to these. the open flow reference
UNITS DISTANCE MICRONS 2000 ;

Coordinates are integers of one two-thousandth of a micron.

Hint: Ask what a coordinate of 1000 means after this line.

DEF (Design Exchange Format) stores coordinates as integers in database units to avoid rounding, so 1000 here is 0.5 microns. The factor also sets the manufacturing grid a tool will snap to, which is why a mismatch between files is a real problem. the open flow reference
DIEAREA ( 0 0 ) ( 200000 200000 ) ; ROW ROW_0 FreePDK45_38x28_10R_NP_162NW_34O 380 2800 N DO 520 BY 1 STEP 380 0 ;

The die outline, and a row repeated across 520 sites.

Hint: The row line ends with a repetition. Ask what it describes.

The row is 520 sites across, stepping in x. DO ... BY ... STEP is how DEF (Design Exchange Format) repeats a row without listing every site: 520 sites across, one row deep, stepping by one site width. N is the orientation, which alternates between rows so neighbouring rows share power rails. the open flow reference
COMPONENTS 1250 ; - _123_ INV_X1 + PLACED ( 12540 28000 ) N ; - _124_ DFF_X1 + FIXED ( 15200 28000 ) FS ; END COMPONENTS

Instances with cell, location, and whether they may be moved.

Hint: Two instances, two different status words. Ask what the difference means to a tool.

The status word decides whether a tool may move it: PLACED means yes, FIXED means no, which is how macros and pre-placed cells are protected. UNPLACED has no coordinates. The orientation, N or FS here, matters because it decides which way the cell's rails and pins face. the open flow reference
NETS 980 ; - clk ( PIN clk ) ( _124_ CK ) + USE CLOCK + ROUTED metal3 ( 12540 28000 ) ( 12540 45000 ) NEW metal4 ( 12540 45000 ) ( 30000 45000 ) ; END NETS

A net's connections and its routed wire segments.

Hint: The net lists connections first, then something else. Ask what NEW starts.

Connections come first, then the wires. A routed net is a list of segments, each with a layer and points; NEW begins a segment that does not continue the previous one, which is how branches are written. USE CLOCK marks what kind of net it is, so tools can treat clocks specially. the open flow reference
SPECIALNETS 2 ; - VDD ( * VDD ) + USE POWER + ROUTED metal1 480 + SHAPE FOLLOWPIN ( 0 2800 ) ( 200000 2800 ) ; END SPECIALNETS

Power and ground, whose wires carry an explicit width and shape.

Hint: Ask what is special: compare the width and the connection list with an ordinary net.

Ordinary nets take their width from the layer's rule; supply wires are drawn wide and are written with their own width and a SHAPE that says what they are, such as FOLLOWPIN for a standard-cell rail. The ( * VDD ) connection means every instance's VDD pin. the open flow reference
PINS 42 ; - clk + NET clk + DIRECTION INPUT + USE SIGNAL + LAYER metal3 ( -70 -70 ) ( 70 70 ) + PLACED ( 45000 0 ) N ; END PINS

A boundary pin's net, direction, shape, and placement.

Hint: Two coordinate pairs appear. Ask which is the shape and which the position.

The shape is relative to the pin's own origin, and PLACED puts that origin on the die. The LAYER rectangle is the shape, and PLACED puts that origin on the die. This is what place_pins writes and what a top level reads to know where a block's connections are. the open flow reference
*D_NET *12 0.0342 *CONN *I *3:ZN O *L *5:A I

A net, its total capacitance, and the pins on it.

Hint: One number on the first line, then a list. Ask what each part is.

*I is an instance pin and *L a load pin with its capacitance. SPEF (Standard Parasitic Exchange Format) describes one net at a time: the total capacitance, the connections (*I for an instance pin, *P for a port), and then the detailed resistance and capacitance network. *L gives a load pin's capacitance. the open flow reference
*NAME_MAP *12 _039_ *3 _897_

A number for every name, so the rest of the file can stay compact.

Hint: Ask why a parasitics file would not simply use the names.

A parasitics file for a real design is enormous, and full hierarchical names repeated on every line would dominate it. The map is declared once and the numbers used afterwards, which is why a SPEF (Standard Parasitic Exchange Format) file is unreadable without its header. the open flow reference
*CAP 1 *12:1 0.00861 2 *12:2 *9:3 0.00234 *RES 1 *12:1 *12:2 3.7

Capacitance to ground and between nets, and node resistance.

Hint: One capacitance line names two nodes. Ask what that means physically.

Resistance runs between the net's internal nodes. A *CAP line with one node is capacitance to ground; with two nodes it is coupling capacitance between two nets, which is what crosstalk analysis needs. *RES lines build the resistive network between the net's internal nodes, which is why a long net is not a single lump. the open flow reference
*T_UNIT 1 NS *C_UNIT 1 PF *R_UNIT 1 OHM

The units every number in the file is expressed in.

Hint: Compare it with Liberty: ask what the file would mean without these lines.

Like Liberty, SPEF (Standard Parasitic Exchange Format) numbers are bare and the header gives their meaning. A file may also carry triplets, written min:typ:max, when one file holds several corners' values at once. the open flow reference
(CELL (CELLTYPE "INV_X1") (INSTANCE _897_) (DELAY (ABSOLUTE (IOPATH A ZN (0.012:0.014:0.019) (0.011:0.013:0.017)))))

The rising and falling delay from A to ZN, as three values.

Hint: Two bracketed groups of three numbers. Ask what each group and each number is.

The three numbers are minimum, typical, and maximum. SDF (Standard Delay Format) carries computed delays per instance, so another tool can time or simulate without repeating delay calculation. The triplet is the standard min, typical, max form, and the two groups are the output's two directions. the open flow reference
(TIMINGCHECK (SETUP D (posedge CK) (0.031)) (HOLD D (posedge CK) (0.012)))

The setup and hold requirements of that instance, annotated from the file.

Hint: Ask what these two lines are, given that they are not delays.

Checks are annotated separately from delays, which is why OpenSTA reports their coverage separately with report_annotated_check. The values replace the library's, so a design timed with an SDF (Standard Delay Format) file may not match one timed from Liberty alone. the open flow reference
(INTERCONNECT _897_/ZN _124_/D (0.004:0.005:0.007))

The wire delay from one instance pin to another.

Hint: Ask which part of a path this covers, given that IOPATH covers the cells.

Cell delays come as IOPATH entries and wire delays as INTERCONNECT entries, one per driver-to-load pair. Annotating both is how a simulation reproduces exactly the timing the analysis saw. the open flow reference
(COND A2 == 1'b0 (IOPATH A1 ZN (0.018:0.021:0.026) (0.016:0.019:0.024)))

A delay that applies only while that condition holds.

Hint: Compare it with the same idea in a Liberty file.

It matches the library's conditional arc for the same pins. A gate's delay depends on its other inputs, so conditional arcs exist in the library and must survive into the annotation. This is what sdf_cond in Liberty is for: it gives the condition in the syntax an SDF (Standard Delay Format) writer needs so the two line up. the open flow reference
read_lef nangate45.tech.lef read_lef nangate45.macro.lef read_verilog gcd.v read_def gcd.def read_spef gcd.spef

Technology, cell shapes, netlist, layout, then the wires' cost.

Hint: Ask what each file adds that the ones before it could not.

In order: what the process allows, what the cells look like, what is connected to what, where everything sits, and what the wires cost. Timing needs one more, the Liberty library, which none of these carry. the open flow reference
LEF (Library Exchange Format) against DEF (Design Exchange Format)

One describes the technology and cells, the other one design.

Hint: One is per library, the other per design. Ask which is which.

LEF (Library Exchange Format) is the library side and DEF (Design Exchange Format) the design side. A LEF (Library Exchange Format) file is written once per technology or library and reused by every design; a DEF (Design Exchange Format) file belongs to one design at one stage. This is why DEF (Design Exchange Format) refers to cells by name and never repeats their shapes. the open flow reference
SPEF (Standard Parasitic Exchange Format) against SDF (Standard Delay Format)

One gives the wires' parasitics, the other computed delays.

Hint: Both describe timing. Ask which one has already been through delay calculation.

SPEF (Standard Parasitic Exchange Format) holds parasitics and SDF (Standard Delay Format) holds delays. With SPEF (Standard Parasitic Exchange Format) the reading tool computes delays itself, so it can re-time after a change. With SDF (Standard Delay Format) the delays are fixed, which is what a gate-level simulation wants. Handing a simulator SPEF (Standard Parasitic Exchange Format), or a timer SDF (Standard Delay Format), works but answers a different question. the open flow reference
write_db against write_def

The database keeps everything; the other is the portable subset.

Hint: Ask which one another vendor's tool can read, and which keeps everything.

DEF (Design Exchange Format) is the portable one. OpenROAD's own database carries the technology, the netlist, the layout, and tool-specific state together, which is why stages hand it along. DEF (Design Exchange Format) carries what other tools can read, and loses whatever has no representation in the format. the open flow reference
UNITS DATABASE MICRONS 2000 ; END UNITS MANUFACTURINGGRID 0.0050 ;

The database resolution, and the coarser grid every shape must land on.

Hint: Two different grids. One is how finely a number can be written, the other what may be made.

A resolution of 2000 means one database unit is half a nanometre, so coordinates are integers. The manufacturing grid is 5 nanometres, and a shape off that grid cannot be made, which is why legalization snaps everything to it. The two numbers are independent. the open flow reference
BUSBITCHARS "[]" ; DIVIDERCHAR "/" ;

The characters that mark a bus bit and a hierarchy level in names.

Hint: Think about how an instance deep in the hierarchy is named in a report.

A pin is out[3] and an instance inside a block is core/reg_1. Tools that disagree about these characters produce names that do not match across files, which is a common cause of a constraint matching nothing. An instance whose real name contains a bracket has to escape it. the open flow reference
LAYER poly TYPE MASTERSLICE ; END poly

A layer that exists in the process but that the router may not use.

Hint: Compare with a layer declared as ROUTING or CUT.

Polysilicon and diffusion appear so that contacts and antenna rules can refer to them, but only ROUTING layers carry routes and only CUT layers carry vias. Declaring a layer with the wrong type is a quick way to make a router either ignore metal or try to route on diffusion. the open flow reference
VIA via1_4 DEFAULT LAYER via1 ; RECT -0.035 -0.035 0.035 0.035 ; END via1_4 VIARULE Via1Array-0 GENERATE LAYER metal1 ; ENCLOSURE 0.035 0.035 ; LAYER via1 ; SPACING 0.15 BY 0.15 ; END Via1Array-0

A fixed via, and a rule for building a via array of any size.

Hint: One is a finished object, the other a recipe.

The named vias are what a router drops between two routing layers. The generate rule says how to build a larger array, giving the metal enclosure on each side and the spacing between cuts, which is what the power grid uses where it needs many cuts to carry current. the open flow reference
LAYER via1 TYPE CUT ; SPACING 0.08 ; RESISTANCE 5 ; END via1

The resistance of one via cut, counted once per cut.

Hint: The number is in ohms, and it is not per unit length.

Five ohms a cut is large next to a short wire, which is why extraction counts vias and why a route that changes layer repeatedly is slower than its length suggests. Doubling the cuts halves the resistance, which is what a via array is for. the open flow reference
SITE FreePDK45_38x28_10R_NP_162NW_34O ; SIZE 0.38 BY 1.4 ;

The cell is one row tall and two sites wide.

Hint: The site is 0.19 by 1.4. Compare that with the size.

Every standard cell is a whole number of sites wide and a whole number of rows tall, which is what lets them abut with the rails lining up. A cell that is two rows tall is a double-height cell, and it must start on a row of the right orientation. the open flow reference
FOREIGN INV_X1 0.0 0.0 ; ORIGIN 0 0 ; SYMMETRY X Y ;

The layout cell this abstract stands for, and the flips that are legal.

Hint: One line points outside the file. The other says how the cell may be turned.

FOREIGN names the real cell in the GDSII (Graphic Design System II) file that this abstract represents, so the two can be merged at streamout. SYMMETRY X Y says the cell may be mirrored about either axis, which is what lets a placer flip cells so that rails abut. the open flow reference
CLASS CORE ; CLASS BLOCK ; CLASS PAD ; CLASS CORE SPACER ;

What kind of object it is, which decides how it may be placed.

Hint: Ask what each one tells the placer to do with the object.

A core cell goes in a row, a block is a hard macro placed by hand or by the macro placer, a pad sits in the ring at the edge of the die, and a spacer is filler. The class also decides whether a cell is counted in the design's area and whether it blocks routing. the open flow reference
PIN VDD DIRECTION INOUT ; USE power ; SHAPE ABUTMENT ; END VDD

A rail that connects by touching its neighbour's rail in the row.

Hint: Ask how this pin gets connected, given that no router ever touches it.

SHAPE ABUTMENT means the shape reaches both edges of the cell, so a row of cells forms a continuous rail with no routing at all. The grid then only has to drop straps onto that rail. A macro's supply pins have no such shape and must be connected explicitly. the open flow reference
library GCD structure INV_X1 boundary layer 11 datatype 0 ( ... ) path layer 10 datatype 0 ( ... ) structure gcd sref INV_X1 at (12540, 28000) reflection

A hierarchy of cells built from polygons and references.

Hint: One structure refers to another rather than repeating it.

A boundary is a filled polygon and a path is a wire with a width. A structure reference places another structure at a point, with an optional flip or rotation, and an array reference repeats one on a grid. This is why a full chip stays a manageable file even with billions of shapes. the open flow reference
metal1 drawing -> layer 11 datatype 0 metal1 pin -> layer 11 datatype 2 metal1 label -> layer 11 datatype 251

Named layers translated into the numbered pairs the file stores.

Hint: The name on the left is what the tools use. Ask what the foundry uses.

GDSII (Graphic Design System II) knows only numbers, so a layer map translates each named purpose into a layer and datatype pair. Getting one wrong sends the foundry a file where pins are drawn as metal or labels are missing, and the rule deck reads the same numbers, so the mistake often passes unnoticed until the checks disagree. the open flow reference
INV_X1 in LEF (Library Exchange Format) INV_X1 in GDSII (Graphic Design System II)

The abstract with pins and blockages, against every polygon in the cell.

Hint: One of the two is what the placer and router read all day.

The abstract carries only what the tools above need: size, pin shapes, and where routing may not go. The layout carries the transistors. They are merged at the end, when the placed abstracts are replaced by the real cells, which is why the two must agree about pin positions exactly. the open flow reference
OASIS (Open Artwork System Interchange Standard)

A newer layout format that stores the same shapes far more compactly.

Hint: Both hold the same layout. Ask what changed between the two formats.

The older format's fixed-width records become bulky at modern densities, where fill alone runs to hundreds of gigabytes. The newer one encodes repetition directly and can shrink a file by a factor of ten. Both are accepted, and the choice is the foundry's. the open flow reference
xor old.gds new.gds -> differences by layer

A shape-by-shape comparison showing only what changed.

Hint: Ask what an empty result would mean.

After a late change, this is how a team proves that only the intended layers moved. A metal-only fix must show differences on the metal and via layers and nothing on the transistor layers, and a fill-only run must show nothing but fill. the open flow reference
module gcd (clk, req_msg, resp_msg); input clk; INV_X1 _897_ (.A(_039_), .ZN(_040_)); DFF_X1 _898_ (.D(_040_), .CK(clk), .Q(resp_msg[3])); endmodule

A gate-level netlist: library cells wired together, and nothing else.

Hint: There is no always block and no operator anywhere in it.

Synthesis turns behaviour into this. Every instance is a cell from the Liberty and LEF (Library Exchange Format) libraries, so the same file can be timed, placed, and routed. It is also what formal equivalence compares against the register-transfer source. the open flow reference
\dpath.a_reg[9]$_DFFE_PP_ ( .D(...) );

An escaped name, so characters that normally mean something are literal.

Hint: Note the leading backslash and where the name ends.

A backslash starts an escaped identifier and a space ends it, which is how a name can contain brackets, dots, or a dollar sign. Scripts that build a name by hand and forget the trailing space are a familiar source of a constraint that silently matches nothing. the open flow reference
.SUBCKT INV_X1 A ZN VDD VSS M0 ZN A VDD VDD PMOS_VTL W=0.415u L=0.05u M1 ZN A VSS VSS NMOS_VTL W=0.415u L=0.05u .ENDS

A transistor-level netlist, which the layout is checked against.

Hint: The instances are not cells. Ask what they are, and which check needs them.

Layout versus schematic extracts devices from the polygons and compares them with this file, so a cell library ships one. It is the reason a design hands off both a gate-level netlist and, for the cells and any analog blocks, a transistor-level one. the open flow reference
gcd.v against gcd.def

The same instances, with connections in one and positions in the other.

Hint: Both list the same instances. Ask what each adds to the list.

A layout exchange file does carry connectivity, but tools treat the netlist as the authority on it and the layout file as the authority on geometry. That is why a flow reads both, and why an instance renamed in one and not the other breaks the link between them. the open flow reference
block.lef block.lib block.gds block.v

The four views a finished block hands up to the level above.

Hint: The level above needs to place, time, and finally merge this block.

The abstract lets the top level place and route around the block, the Liberty model lets it be timed without its internals, the layout is merged at streamout, and the netlist supports layout versus schematic. A hard macro such as a memory arrives the same way. the open flow reference
TRACKS X 190 DO 193 STEP 380 LAYER metal1 ; TRACKS Y 140 DO 262 STEP 280 LAYER metal1 ;

The routing grid: 193 vertical tracks from 190, every 380 database units.

Hint: Three numbers: where they start, how many, and how far apart.

With 2000 database units to the micron, the step is 0.19 microns. A router places wire centres on these tracks, so the count is the hard limit on how many wires cross the block on that layer. The two directions are given separately because each layer has a preferred one. the open flow reference
- FILLER_0_1 FILLCELL_X32 + SOURCE DIST + PLACED ( 2660 2800 ) N ; - _504_ NAND2_X1 + PLACED ( 12540 28000 ) FS ;

Which stage created the instance, and the orientation it sits at.

Hint: One instance says where it came from, and the other says how it is turned.

SOURCE DIST marks a cell added by the tool for distribution, such as filler; the alternatives include netlist, timing, and user. The orientation FS is flipped about the horizontal axis, which is how cells in an odd row line their supply rails up with the row below. the open flow reference
NONDEFAULTRULES 1 ; - CTS_NDR_0 + LAYER metal1 WIDTH 140 SPACING 280 + LAYER metal4 WIDTH 280 SPACING 560 ; - clk ( PIN clk ) ( clkbuf_0_clk A ) + USE CLOCK + NONDEFAULTRULE CTS_NDR_0

A rule giving some nets wider wires and more space, here the clock.

Hint: Compare the widths and spacings against what the technology allows as a minimum.

Widening a clock wire lowers its resistance, and doubling its spacing cuts coupling from neighbours, which protects the clock from crosstalk it would otherwise pick up. The cost is routing area, so the rule is applied to the nets that need it rather than to everything. the open flow reference
- _002_ ( _597_ A2 ) ( _595_ A2 ) + USE SIGNAL + ROUTED metal3 ( 31350 49140 ) ( 40090 * ) NEW metal2 ( 40850 48860 ) ( * 49140 ) NEW metal1 ( 31350 51940 ) via1_4

Wire segments, where an asterisk repeats the unchanged coordinate.

Hint: The asterisk stands for a coordinate. Ask which one.

A segment runs from one point to another, and because wires are straight only one coordinate changes, so the other is written as an asterisk. NEW starts a segment that does not continue from the last one, and a via name in place of an end point drops that via at the point given. the open flow reference
*CAP 3 *1158:QN 0.00013985 4 *3:10 0.000151825 6 *742:A2 *745:A2 2.94435e-05 12 *3:10 *943:A3 0.000127816

Capacitance to ground on one node, or coupling between two nodes.

Hint: Some entries name one node and some name two. Ask what the second node is.

A two-node entry is the coupling between this net and its neighbour, and it is the raw material of crosstalk analysis. Entry 12 couples an internal node of this net to a pin of another, and it is larger than some of this net's own grounded capacitance. the open flow reference
*RES 1 *1158:QN *3:10 31.1072 2 *3:10 *744:A2 10 3 *3:10 *742:A2 12.3571

The net as a resistor network, branching at an internal node.

Hint: Follow the node names: one of them appears in every line.

*3:10 is an internal node of net 3, where the wire splits toward two loads. The driver reaches it through 31 ohms, and each load hangs off it through its own resistance. A timer solves this network with the capacitances to get a delay to each load, which is why the two loads see different delays. the open flow reference
(SDFVERSION "3.0") (DESIGN "gcd") (VOLTAGE 1.100::1.100) (PROCESS "1.000::1.000") (TEMPERATURE 25.000::25.000) (TIMESCALE 1ns)

The corner the delays hold for, and the unit they are written in.

Hint: Ask what would have to change for a second file to be needed.

One file is one corner. A simulation at another voltage or temperature needs its own, which is why a regression annotates a different file for each corner it runs. The timescale sets what a bare number means, so reading a file that assumes nanoseconds as picoseconds is silently wrong. the open flow reference
(IOPATH A1 ZN (0.023::0.023) (0.022::0.022)) (SETUP (posedge D) (posedge CK) (0.030::0.032))

Minimum and maximum for each value, with rise and fall given separately.

Hint: Count the numbers in each bracket, and count the brackets.

The format allows three values separated by colons, but a missing middle one leaves the pair written here. The first bracket of an arc is the rising output and the second the falling. For a check, the two values are the fast and slow versions of the same requirement. the open flow reference