Explore / Methods & Algorithms / Timing Analysis / Elmore Delay

Elmore Delay

Timing Analysis foundational 1948 Elmore; Rubinstein, Penfield, Horowitz closed-form and additive pessimistic on real wires

The formula

For an RC (Resistance-Capacitance) tree driven at the root, the Elmore delay to sink k is:

T(k) = Σ over nodes i of R(path to k ∩ path to i) · C(i)
  • T(k) Elmore delay estimate from the root to sink k
  • i runs over every node of the RC (Resistance-Capacitance) tree
  • R(...) resistance shared by the root-to-k and root-to-i paths
  • C(i) capacitance hanging at node i

read as: walk the resistive path from root to k; each resistance R carries a charging burden equal to all capacitance C downstream of it, wherever it hangs. Equivalently, it is the first moment of the network's impulse response, the mean of the delay distribution used as if it were the delay. Derived by Elmore in 1948 for amplifiers, it entered VLSI (Very Large Scale Integration) when Rubinstein, Penfield, and Horowitz gave the tree formulation and bounds in 1983.

Why algorithms love it

Closed form, linear-time for all sinks in one traversal, and additive: extend a wire and delay updates incrementally, which is exactly what an inner optimization loop needs when it evaluates thousands of candidate topologies. It is also provably conservative in the useful direction for RC trees (an upper bound on 50 percent delay), and, most importantly, it ranks alternatives with high fidelity: the topology Elmore prefers is almost always the topology accurate simulation prefers.

Its limits

Resistive shielding is invisible to it (downstream capacitance behind big resistance counts fully, so it overestimates, sometimes badly on resistive nets), slew is not modeled, and inductance does not exist. Sign-off therefore moved to moment matching (next page) and library- characterized gate models decades ago.

Where you meet it today

Inside zero-skew clock construction (the Clock Tree Synthesis catalog's merge equations are Elmore algebra), inside van Ginneken buffering, in placement and routing cost functions, and in every back-of-envelope wire-delay estimate anyone scribbles.

References and further reading