Gate Sizing (Logical Effort and Lagrangian Methods)
The theory: logical effort
Model a gate's delay as
glogical effort: how much worse than an inverter the gate's topology driveshelectrical effort: output load divided by input capacitancepparasitic delay: the gate's intrinsic, load-independent cost
Along a path, total delay is minimized when every stage bears the same stage effort, the geometric mean of the path's total effort, with optimal stage effort near 4 (whence the folklore fanout-of-four rule and the formula for how many stages a heavy load deserves). Ten minutes of algebra explains buffer chains, why reordering logic helps, and roughly how big everything should be, the single most useful piece of theory in a circuit designer's pocket.
The optimization
Real sizing is a global problem: gates share loads, so sizes couple. With continuous sizes and Elmore-style delays the problem is posynomial, convex after a change of variables, so exact optimums are computable (the TILOS line: greedy sensitivity sizing guided by this structure; later, full geometric programming). Production methods must instead pick from a discrete library of drive strengths and thresholds under characterized (non-posynomial) delays, so modern sizers use Lagrangian relaxation: dualize the timing constraints, let per-arc multipliers price criticality, then sweep the netlist choosing each gate's cheapest size given its prices, iterating multiplier updates, scalable to millions of cells and the shape of most published industrial sizers.
Where you meet it today
Every synthesis and physical-synthesis tool's sizing passes (OpenROAD's resizer among them), power-recovery loops that downsize off-critical gates, and interviews, where logical effort is the canonical 'show me you understand delay' topic.