Statistical Static Timing Analysis

The idea

Corners answer 'does the chip work if everything is slow?', a question no die ever poses; process variation is partly random and per-device, and worst-casing every device simultaneously is both pessimistic (independent randomness averages out) and, for hold checks, potentially optimistic (correlations cut both ways). Statistical static timing analysis replaces each delay with a random variable. The canonical first-order form writes every timing quantity as a nominal value plus sensitivities to shared global sources of variation (per-layer, per-region, per-parameter) plus an independent random term. Addition of such forms is exact and trivial; the crux is max: the maximum of two Gaussians is not Gaussian, so block-based engines re-approximate each max back into canonical form using Clark's classical moment formulas, keeping correlation tracking (two paths sharing a common prefix stay properly correlated through the shared sensitivities). Two sweeps as usual, and the output is a slack distribution per endpoint: parametric yield versus frequency rather than one brittle number.

Adoption

A wave of 2000s research promised statistical sign-off; industry mostly settled elsewhere. Foundry statistical models are hard to get and validate, methodology inertia is real, and cheaper compromises (pessimism-controlled corners, advanced on-chip-variation derating tables, which are themselves statistical data in disguise) captured much of the benefit. Statistical engines thrive where the question is genuinely distributional: memory characterization, yield-versus- frequency binning, variation-aware library and clock analysis.

Where you meet it today

Inside advanced on-chip-variation methodologies (learned or table-based derates), vendor statistical modes, and any conversation about why sign-off corners keep multiplying.