What you are looking at
A block with four memory macros (think SRAM (Static Random-Access Memory) arrays), about 130,000 square micrometers of standard-cell logic, and three groups of input/output pins on the die edge. Each macro has a colored pin edge: its 64-bit data bus leaves from there to a small controller (the matching colored dot), and every controller talks to the central hub, which also talks to the input/output pins.
Drag a macro to move it. Click it to turn it a quarter turn, which moves its pin edge. The dashed ring around each macro is its halo: a keep-out band where no standard cell may sit, so the cells never crowd the macro's pins. The dots move on their own: each controller settles at the bit-weighted average of what it connects to, the same pull a real placer will exert later.
Utilization and aspect ratio
Core utilization is (cell area + macro area) ÷ core area. It is the first number every floorplan script sets, and it sizes the die: at 70% the core is 30% whitespace. Push it toward 90% and the die shrinks, so wires get shorter, but the cells pack tighter and their local wiring eats the tracks that longer wires need. That is the core trade of floorplanning: area and wirelength against routability. Aspect ratio (height ÷ width) reshapes the die; macros keep their relative position, which can make them collide, so watch for red outlines.
Two congestion forecasts
Nothing is routed yet at floorplan time, so the heat map is a forecast of routing demand ÷ routing supply in each 20 micrometer bin. Supply drops above a macro, because the macro owns the lower metal layers and only the upper layers pass over it. Two forecasts are offered, and the gap between them is itself a lesson.
RUDY (Rectangular Uniform wire DensitY), from Spindler and Johannes at DATE (Design, Automation and Test in Europe) 2007, smears each connection's wire evenly over its bounding box. It is nearly free to compute, which is why placers use it inside their inner loops. But it cannot see obstacles or direction: it does not know a wire will have to squeeze through a gap.
The trial global route actually routes every connection with L-shaped and Z-shaped patterns on the bin grid, pricing each bin edge by how full it already is, then rips up and reroutes twice. It detours around full regions and reports the busier direction of each bin, so it sees a jammed channel that RUDY (Rectangular Uniform wire DensitY) averages away. Load Tight channel and flip between the two.
The rules of thumb, made visible
- Macros go to the edges. In the middle they chop the core into pieces, and every wire between the pieces has to cross them on the few tracks above. Notice that the wirelength barely changes between Macros in the middle and Macros on the edges: what the middle placement costs is congestion, not length.
- Pins face the core. A pin edge against the die wall leaves no room to reach it, and every bit of the bus has to wrap around the macro. Pins facing the wall costs about a quarter more wire.
- A channel is either wide or absent. Two macros a halo-width or two apart leave a gap too narrow for useful logic but still in the path of every wire that wants to cross. Either abut the macros or open the gap properly.
- Leave whitespace. The same floorplan that routes at 70% utilization can fail at 90%.
From this toy to a real flow
A real block has dozens to hundreds of macros, a netlist of millions of cells, a power grid, timing constraints, and ten or more metal layers. In OpenROAD the die comes from the utilization and aspect ratio you set here, and the macros are placed by Hier-RTLMP (Hierarchical Register Transfer Level Macro Placer), which has commands for exactly the halos and channels on this page. The congestion map that counts comes later, from global routing after placement; both forecasts here are floorplan-time guesses at it.
Things to try
- Start from Macros in the middle and drag the four memories into the corners, pin edges facing in. Watch the red bins disappear.
- On Macros on the edges, raise utilization from 70% to 90% on the trial global route. Wirelength falls while congestion climbs.
- On Tight channel, compare the two forecasts. Then click Memory A and Memory B so their pins point down into the core, and drag them together until they touch: no channel, no jam.
- Turn on Show wires in trial-route mode to see where the router actually sent each bus.